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ISLPED
1996
ACM
70views Hardware» more  ISLPED 1996»
14 years 27 days ago
Circuit techniques for low-power CMOS GSI
Azeez J. Bhavnagarwala, Vivek De, Blanca Austin, J...
ISLPED
1996
ACM
78views Hardware» more  ISLPED 1996»
14 years 27 days ago
Gate-level current waveform simulation of CMOS integrated circuits
We present a new gate-level approach to current simulation. We use a symbolic model of current pulses that takes accurately into account the dependence on the switching conditions...
Alessandro Bogliolo, Luca Benini, Giovanni De Mich...
ISLPED
1996
ACM
51views Hardware» more  ISLPED 1996»
14 years 27 days ago
Practical performance/power alternatives within an existing CMOS technology generation
Kerry Bernstein, John E. Bertsch, William F. Clark...
ISLPED
1996
ACM
91views Hardware» more  ISLPED 1996»
14 years 27 days ago
Energy minimization using multiple supply voltages
We present a dynamic programming technique for solving the multiple supply voltage scheduling problem in both nonpipelined and functionally pipelined data-paths. The scheduling pro...
Jui-Ming Chang, Massoud Pedram
ISLPED
1996
ACM
112views Hardware» more  ISLPED 1996»
14 years 27 days ago
Data driven signal processing: an approach for energy efficient computing
Anantha Chandrakasan, Vadim Gutnik, Thucydides Xan...
ISLPED
1996
ACM
68views Hardware» more  ISLPED 1996»
14 years 27 days ago
Energy-recovery CMOS for highly pipelined DSP designs
We compare the frequency-versus-power dissipation performance of two energy-recovery CMOS implementations to that of a conventional, supply-voltage-scaled design. The application ...
William C. Athas, W.-C. Liu, Lars J. Svensson
VTS
1996
IEEE
76views Hardware» more  VTS 1996»
14 years 27 days ago
Test point insertion based on path tracing
This paper presents an innovative method for inserting test points in the circuit-under-test to obtain complete fault coverage for a specified set of test patterns. Rather than us...
Nur A. Touba, Edward J. McCluskey
VTS
1996
IEEE
80views Hardware» more  VTS 1996»
14 years 27 days ago
Improving the accuracy of diagnostics provided by fault dictionaries
John W. Sheppard, William R. Simpson
VTS
1996
IEEE
111views Hardware» more  VTS 1996»
14 years 27 days ago
Synthesis-for-scan and scan chain ordering
Designing a testable circuit is often a two step process. First, the circuit is designed to conform to the functional specifications. Then, the testability aspects are added. By t...
Robert B. Norwood, Edward J. McCluskey
VTS
1996
IEEE
112views Hardware» more  VTS 1996»
14 years 27 days ago
Optimal voltage testing for physically-based faults
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
Yuyun Liao, D. M. H. Walker