In this paper, we formulate the problem of topology constrained rectilinear block packing in layout reuse. A speci c class of rectilinear shaped blocks, ordered convex rectilinear...
In very deep-submicron VLSI, certain manufacturing steps – notably optical exposure, resist development and etch, chemical vapor deposition and chemical-mechanical polishing (CM...
Andrew B. Kahng, Gabriel Robins, Anish Singh, Huij...
—The greedy wire-sizing algorithm (GWSA) has been experimentally shown to be very efficient, but no mathematical analysis on its convergence rate has ever been reported. In this...
It is shown that the oorplan area minimization problem can be formulated as a convex programming problem with the numbers of variables and constraints signi cantly less than those...
In this paper, we present a new analytical approach for computing the ramp response of an RLC interconnect line with a pure capacitive load. The approach is based on the two-port ...
This paper describes an important new facility for timing-driven design applications within the new CHDStd standard for a SEMATECH design system for large complex chips. We first ...
S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, ...
Wirelength estimation in VLSI layout is fundamental to any pre-detailed routing estimate of timing or routability. In this paper, we develop e cient wirelength estimation techniqu...
Andrew E. Caldwell, Andrew B. Kahng, Stefanus Mant...
In this paper, we formulate a new class of optimization problem, named the general CH-posynomial program, and reveal the general dominance property. We propose an efcient algorith...