ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Optimizing the performance of a multi-core microprocessor within a power budget has recently received a lot of attention. However, most existing solutions are centralized and cann...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Since 2005, processor designers have increased core counts to exploit Moore’s Law scaling, rather than focusing on single-core performance. The failure of Dennard scaling, to wh...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Emerging memory technologies such as STT-RAM, PCRAM, and resistive RAM are being explored as potential replacements to existing on-chip caches or main memories for future multi-co...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Performance-asymmetric multi-cores consist of heterogeneous cores, which support the same ISA, but have different computing capabilities. To maximize the throughput of asymmetric...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
As the number of cores on a single-chip grows, scalable barrier synchronization becomes increasingly difficult to implement. In software implementations, such as the tournament ba...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
As we move to large manycores, the hardware-based global checkpointing schemes that have been proposed for small shared-memory machines do not scale. Scalability barriers include ...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Inclusive last-level caches (LLCs) waste precious silicon estate due to cross-level replication of cache blocks. As the industry moves toward cache hierarchies with larger inner l...
ISCA
2011
IEEE
12 years 10 months ago
2011
IEEE
In recent years, the increasing number of processor cores and limited increases in main memory bandwidth have led to the problem of the bandwidth wall, where memory bandwidth is b...
HPCA
2011
IEEE
12 years 10 months ago
2011
IEEE
Queues are commonly used in multithreaded programs for synchronization and communication. However, because software queues tend to be too expensive to support finegrained paralle...