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ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
14 years 1 months ago
Execution Characteristics of Desktop Applications on Windows NT
This paper examines the performance of desktop applications running on the Microsoft Windows NT operating system on Intel x86 processors, and contrasts these applications to the p...
Dennis C. Lee, Patrick Crowley, Jean-Loup Baer, Th...
ISCA
1998
IEEE
108views Hardware» more  ISCA 1998»
14 years 1 months ago
Pipeline Gating: Speculation Control for Energy Reduction
Branch prediction has enabled microprocessors to increase instruction level parallelism (ILP) by allowing programs to speculatively execute beyond control boundaries. Although spe...
Srilatha Manne, Artur Klauser, Dirk Grunwald
ISCA
1998
IEEE
136views Hardware» more  ISCA 1998»
14 years 1 months ago
Exploiting Spatial Locality in Data Caches Using Spatial Footprints
Modern cache designs exploit spatial locality by fetching large blocks of data called cache lines on a cache miss. Subsequent references to words within the same cache line result...
Sanjeev Kumar, Christopher B. Wilkerson
ISCA
1998
IEEE
143views Hardware» more  ISCA 1998»
14 years 1 months ago
Lockup-Free Instruction Fetch/Prefetch Cache Organization
In the past decade. there has been much literature describing various cache organizatrons that exploit general programming idiosyncrasies to obtain maxrmum hit rate (the probabili...
David Kroft
ISCA
1998
IEEE
102views Hardware» more  ISCA 1998»
14 years 1 months ago
The DASH Prototype: Implementation and Performance
Daniel Lenoski, James Laudon, Truman Joe, David Na...
ISCA
1998
IEEE
104views Hardware» more  ISCA 1998»
14 years 1 months ago
Selective Eager Execution on the PolyPath Architecture
Control-flow misprediction penalties are a major impediment to high performance in wide-issue superscalar processors. In this paper we present Selective Eager Execution (SEE), an ...
Artur Klauser, Abhijit Paithankar, Dirk Grunwald
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
14 years 1 months ago
Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...
Kimberly Keeton, David A. Patterson, Yong Qiang He...
ISCA
1998
IEEE
134views Hardware» more  ISCA 1998»
14 years 1 months ago
Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor
Much of the improvement in computer performance over the last twenty years has come from faster transistors and architectural advances that increase parallelism. Historically, par...
Stephen W. Keckler, William J. Dally, Daniel Maski...
ISCA
1998
IEEE
102views Hardware» more  ISCA 1998»
14 years 1 months ago
Dynamic History-length Fitting: A Third Level of Adaptivity for Branch Prediction
Accurate branch prediction is essential for obtaining high performance in pipelined superscalar processors that execute instructions speculatively. Some of the best current predic...
Toni Juan, Sanji Sanjeevan, Juan J. Navarro