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ISCA
1998
IEEE
135views Hardware» more  ISCA 1998»
14 years 1 months ago
Confidence Estimation for Speculation Control
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and o...
Dirk Grunwald, Artur Klauser, Srilatha Manne, Andr...
ISCA
1998
IEEE
142views Hardware» more  ISCA 1998»
14 years 1 months ago
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work
Pipeline flushes due to branch mispredictions is one of the most serious problems facing the designer of a deeply pipelined, superscalar processor. Many branch predictors have bee...
Marius Evers, Sanjay J. Patel, Robert S. Chappell,...
ISCA
1998
IEEE
118views Hardware» more  ISCA 1998»
14 years 1 months ago
Active Messages: A Mechanism for Integrated Communication and Computation
The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without ...
Thorsten von Eicken, David E. Culler, Seth Copen G...
ISCA
1998
IEEE
126views Hardware» more  ISCA 1998»
14 years 1 months ago
Switcherland: A QoS Communication Architecture for Workstation Clusters
Computer systems have become powerful enough to process continuous data streams such as video or animated graphics. While processing power and communication bandwidth of today...
Hans Eberle, Erwin Oertli
ISCA
1998
IEEE
137views Hardware» more  ISCA 1998»
14 years 1 months ago
Accurate Indirect Branch Prediction
Indirect branch prediction is likely to become increasingly important in the future because indirect branches occur more frequently in object-oriented programs. With misprediction ...
Karel Driesen, Urs Hölzle
ISCA
1998
IEEE
107views Hardware» more  ISCA 1998»
14 years 1 months ago
Memory Dependence Prediction Using Store Sets
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
George Z. Chrysos, Joel S. Emer
ISCA
1998
IEEE
145views Hardware» more  ISCA 1998»
14 years 1 months ago
Multi-Level Texture Caching for 3D Graphics Hardware
Traditional graphics hardware architectures implement what we call the push architecture for texture mapping. Local memory is dedicated to the accelerator for fast local retrieval...
Michael Cox, Narendra Bhandri, Michael Shantz
ISCA
1998
IEEE
122views Hardware» more  ISCA 1998»
14 years 1 months ago
Design Choices in the SHRIMP System: An Empirical Study
The SHRIMP cluster-computing system has progressed to a point of relative maturity; a variety of applications are running on a 16-node system. We have enough experience to underst...
Matthias A. Blumrich, Richard Alpert, Yuqun Chen, ...
ISCA
1998
IEEE
151views Hardware» more  ISCA 1998»
14 years 1 months ago
Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture
Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques whic...
David I. August, Daniel A. Connors, Scott A. Mahlk...
ISCA
1998
IEEE
144views Hardware» more  ISCA 1998»
14 years 1 months ago
Declustered Disk Array Architectures with Optimal and Near-Optimal Parallelism
This paper investigates the placement of data and parity on redundant disk arrays. Declustered organizations have been traditionally used to achieve fast reconstruction of a faile...
Guillermo A. Alvarez, Walter A. Burkhard, Larry J....