ISSS
1998
IEEE
14 years 1 months ago
1998
IEEE
Commonly used scheduling algorithms in high-level synthesis are not capable of sharing resources across process boundaries. This results in the usage of at least one resource per ...
ISSS
1998
IEEE
14 years 1 months ago
1998
IEEE
In this paper, we propose the target board architecture of a rapid prototyping embedded system based on hardware software codesign. The target board contains a TMS320C30 DSP proce...
ISSS
1998
IEEE
14 years 1 months ago
1998
IEEE
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
ISSS
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper describes a methodology for synthesizing the data-path of a Very Long Instruction Word (VLIW) based Video Signal Processor (VSP). Offering both performance and programm...
ISSS
1998
IEEE
14 years 1 months ago
1998
IEEE
With the decreasing feature sizes during VLSI fabrication and the dominance of interconnect delay over that of gates, control logic and wiring no longer have a negligible impact o...
ISMVL
1998
IEEE
14 years 1 months ago
1998
IEEE
The use of Look-Up Tables (LUTs) is extended from binary to multiple-valued logic (MVL) circuits. A multiplevalued LUT can be implemented using both current-mode and voltage-mode ...
ISMVL
1998
IEEE
14 years 1 months ago
1998
IEEE
Decision diagrams are the state-of-the-art representation for logic functions, both binary and multiple-valued. Here we consider issues regarding the efficient implementation of a...
ISMVL
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper provides a brief overview of semiconductor memory design from the perspective of the impact multiplevalued circuit techniques are making on modern day implementations. ...
ISCA
1998
IEEE
14 years 1 months ago
1998
IEEE
As the issue rate and depth of pipelining of high performance Superscalar processors increase, the importance of an excellent branch predictor becomes more vital to delivering the...
ISCA
1998
IEEE
14 years 1 months ago
1998
IEEE
This paper presents Threaded Multi-Path Execution (TME), which exploits existing hardware on a Simultaneous Multithreading (SMT) processor to speculatively execute multiple paths ...