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ISCA
1998
IEEE
139views Hardware» more  ISCA 1998»
14 years 1 months ago
Simultaneous Multithreading: Maximizing On-Chip Parallelism
This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar's multiple functional units in a si...
Dean M. Tullsen, Susan J. Eggers, Henry M. Levy
ISCA
1998
IEEE
117views Hardware» more  ISCA 1998»
14 years 1 months ago
Increasing TLB Reach Using Superpages Backed by Shadow Memory
Mark R. Swanson, Leigh Stoller, John B. Carter
ISCA
1998
IEEE
113views Hardware» more  ISCA 1998»
14 years 1 months ago
Flexible Use of Memory for Replication/Migration in Cache-Coherent DSM Multiprocessors
Vijayaraghavan Soundararajan, Mark Heinrich, Ben V...
ISCA
1998
IEEE
128views Hardware» more  ISCA 1998»
14 years 1 months ago
Analytic Evaluation of Shared-memory Systems with ILP Processors
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mar...
ISCA
1998
IEEE
122views Hardware» more  ISCA 1998»
14 years 1 months ago
Multiscalar Processors
Gurindar S. Sohi, Scott E. Breach, T. N. Vijaykuma...
ISCA
1998
IEEE
155views Hardware» more  ISCA 1998»
14 years 1 months ago
A Study of Branch Prediction Strategies
In high-performance computer systems, performance losses due to conditional branch instructions can be minimized by predicting a branch outcome and fetching, decoding, and/or issu...
James E. Smith
ISCA
1998
IEEE
128views Hardware» more  ISCA 1998»
14 years 1 months ago
Modeling Program Predictability
Basic properties of program predictability
Yiannakis Sazeides, James E. Smith
ISCA
1998
IEEE
115views Hardware» more  ISCA 1998»
14 years 1 months ago
Improving the Throughput of a Pipeline by Insertion of Delays
Janak H. Patel, Edward S. Davidson
ISCA
1998
IEEE
119views Hardware» more  ISCA 1998»
14 years 1 months ago
Using Prediction to Accelerate Coherence Protocols
Most large shared-memory multiprocessors use directory protocols to keep per-processor caches coherent. Some memory references in such systems, however, suffer long latencies for ...
Shubhendu S. Mukherjee, Mark D. Hill
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
14 years 1 months ago
Active Pages: A Computation Model for Intelligent Memory
Microprocessors and memory systems su er from a growing gap in performance. We introduce Active Pages, a computation model which addresses this gap by shifting data-intensive comp...
Mark Oskin, Frederic T. Chong, Timothy Sherwood