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ACSD
1998
IEEE
90views Hardware» more  ACSD 1998»
14 years 1 months ago
Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation
This paper makes the idea of memory shadowing [5] applicable to symbolic ternary simulation. Memory shadowing, an extension of Burch and Dill's pipeline verification method [...
Miroslav N. Velev, Randal E. Bryant
ACSD
1998
IEEE
105views Hardware» more  ACSD 1998»
14 years 1 months ago
Visual Formalisms Revisited
The development of an interactive application is a complex task that has to consider data, behavior, intercommunication, architecture and distribution aspects of the modeled syste...
Radu Grosu, Gheorghe Stefanescu, Manfred Broy
ACSD
1998
IEEE
101views Hardware» more  ACSD 1998»
14 years 1 months ago
A True Concurrency Semantics for ET-LOTOS
One of the central objectives of the LOTOS restandardisation activity is to de ne an enhanced LOTOS language which supports real-time speci cation. The timed extension is based up...
Howard Bowman, Joost-Pieter Katoen
ACSD
1998
IEEE
125views Hardware» more  ACSD 1998»
14 years 1 months ago
Hierarchical Concurrent Finite State Machines in Ptolemy
We implement a finite state machine (FSM) domain for specifying and simulating control functionality of a system within the Ptolemy software environment. The FSM domain is success...
Bilung Lee, Edward A. Lee
ACSD
1998
IEEE
113views Hardware» more  ACSD 1998»
14 years 1 months ago
Modeling and Analyzing Interorganizational Workflows
Today's corporations often must operate across organizational boundaries. Phenomena such as electronic commerce, extended enterprises, and the Internet stimulate cooperation ...
Wil M. P. van der Aalst
ACSD
1998
IEEE
121views Hardware» more  ACSD 1998»
14 years 1 months ago
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings
State coding conflict detection is a fundamental part of synthesis of asynchronous concurrent systems from their specifications as Signal Transition Graphs (STGs), which are a spe...
Alex Kondratyev, Jordi Cortadella, Michael Kishine...
VTS
1999
IEEE
68views Hardware» more  VTS 1999»
14 years 1 months ago
A Test Point Insertion Algorithm for Mixed-Signal Circuits
This paper presents an algorithm based on testability measurement for test point insertion of mixed-signal circuits. Two transfer function models compatible with analog models are...
Jinyan Zhang, Sam D. Huynh, Mani Soma
VTS
1999
IEEE
66views Hardware» more  VTS 1999»
14 years 1 months ago
A New Bare Die Test Methodology
1 While multichip module technology has been developed for high performance IC applications, the technology is not widely adopted due to economical reasons. One of the reasons that...
Zao Yang, K.-T. Cheng, K. L. Tai
VTS
1999
IEEE
88views Hardware» more  VTS 1999»
14 years 1 months ago
Multiple Design Error Diagnosis and Correction in Digital VLSI Circuits
Andreas G. Veneris, Ibrahim N. Hajj, Srikanth Venk...
VTS
1999
IEEE
83views Hardware» more  VTS 1999»
14 years 1 months ago
PADded Cache: A New Fault-Tolerance Technique for Cache Memories
This paper presents a new fault-tolerance technique for cache memories. Current fault-tolerance techniques for caches are limited either by the number of faults that can be tolera...
Philip P. Shirvani, Edward J. McCluskey