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ATS
1998
IEEE
84views Hardware» more  ATS 1998»
14 years 1 months ago
A BIST Structure to Test Delay Faults in a Scan Environment
Patrick Girard, Christian Landrault, V. Moreda, Se...
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
14 years 1 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
ATS
1998
IEEE
106views Hardware» more  ATS 1998»
14 years 1 months ago
A Test Pattern Generation Algorithm Exploiting Behavioral Information
This paper aims at broadening the scope of hierarchical ATPG to the behavioral-level The main problem of using behavioral information for ATPG is the mismatch of timing models bet...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
ASYNC
1998
IEEE
110views Hardware» more  ASYNC 1998»
14 years 1 months ago
Analyzing Specifications for Delay-Insensitive Circuits
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays inc...
Tom Verhoeff
ASYNC
1998
IEEE
100views Hardware» more  ASYNC 1998»
14 years 1 months ago
An Implicit Method for Hazard-Free Two-Level Logic Minimization
None of the available minimizers for exact 2-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to heuristic...
Michael Theobald, Steven M. Nowick
ASYNC
1998
IEEE
71views Hardware» more  ASYNC 1998»
14 years 1 months ago
Towards Asynchronous A-D Conversion
Analogue to digital (A-D) converters with a xed conversion time are subject to errors due to metastability. These errors will occur in all converter designs with a bounded time fo...
D. J. Kinniment, Alexandre Yakovlev, Fei Xia, B. G...
ASYNC
1998
IEEE
91views Hardware» more  ASYNC 1998»
14 years 1 months ago
Predicting Performance of Micropipelines Using Charlie Diagrams
A technique is presented to predict the performance behavior of control circuits for a linear FIFO. The control circuit consists of a linear chain of RendezVous elements, also cal...
Jo C. Ebergen, Scott Fairbanks, Ivan E. Sutherland
ASYNC
1998
IEEE
84views Hardware» more  ASYNC 1998»
14 years 1 months ago
Average-Case Optimized Transistor-Level Technology Mapping of Extended Burst-Mode Circuits
We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-element (gC) implementations of extended burst-mode asynchronous controllers. Averag...
Kevin W. James, Kenneth Y. Yun
ASYNC
1998
IEEE
122views Hardware» more  ASYNC 1998»
14 years 1 months ago
A Fast Asynchronous Huffman Decoder for Compressed-Code Embedded Processors
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs a...
Martin Benes, Steven M. Nowick, Andrew Wolfe