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VTS
1999
IEEE
114views Hardware» more  VTS 1999»
14 years 1 months ago
Partial Scan Using Multi-Hop State Reachability Analysis
Sequential test generators fail to yield tests for some stuck-at-faults because they are unable to reach certain states necessary for exciting propagating these target faults. Add...
Sameer Sharma, Michael S. Hsiao
VTS
1999
IEEE
76views Hardware» more  VTS 1999»
14 years 1 months ago
Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM
Maurizio Rebaudengo, Matteo Sonza Reorda
VTS
1999
IEEE
81views Hardware» more  VTS 1999»
14 years 1 months ago
Simulation-Based Design Error Diagnosis and Correction in Combinational Digital Circuits
This paper describes an approach to design error diagnosis and correction in combinational digital circuits. Our approach targets small errors introduced during the design process...
Debashis Nayak, D. M. H. Walker
VTS
1999
IEEE
125views Hardware» more  VTS 1999»
14 years 1 months ago
Error Detecting Refreshment for Embedded DRAMs
This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test c...
Sybille Hellebrand, Hans-Joachim Wunderlich, Alexa...
VTS
1999
IEEE
106views Hardware» more  VTS 1999»
14 years 1 months ago
RT-level TPG Exploiting High-Level Synthesis Information
High-level test pattern generation is today a widely investigated research topic. The present paper proposes a fully automated, simulation-based ATPG system, to address test patte...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto
VTS
1999
IEEE
108views Hardware» more  VTS 1999»
14 years 1 months ago
Adaptive Techniques for Improving Delay Fault Diagnosis
This paper presents adaptive techniques for improving delay fault diagnosis. These techniques reduce the search space for direct probing which can save a lot of time during failur...
Jayabrata Ghosh-Dastidar, Nur A. Touba
VTS
1999
IEEE
100views Hardware» more  VTS 1999»
14 years 1 months ago
Low-Cost On-Line Test for Digital Filters
A low-cost on-line test scheme for digital filters is proposed. The scheme uses an invariant of the digital filter, the frequency response at specific points, in order to detect p...
Ismet Bayraktaroglu, Alex Orailoglu
VTS
1999
IEEE
71views Hardware» more  VTS 1999»
14 years 1 months ago
Test Generation for Ground Bounce in Internal Logic Circuitry
Ground bounce in internal circuitry is becoming an important design validation and test issue. In this paper a new circuit model for ground bounce in internal circuitry is propose...
Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer
FPL
1999
Springer
115views Hardware» more  FPL 1999»
14 years 1 months ago
A Runtime Reconfigurable Implementation of the GSAT Algorithm
Wong Hiu Yung, Wing Seung Yuen, Kin-Hong Lee, Phil...
FPL
1999
Springer
88views Hardware» more  FPL 1999»
14 years 1 months ago
Accelerating Boolean Implications with FPGAs
Kolja Sulimma, Dominik Stoffel, Wolfgang Kunz