DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper presents a technique for glitch power minimization in combinational circuits. The total number of glitches is reduced by replacing some existing gates with functionally...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
This paper presents a new Design for Testability (DFT) technique for Current-Mode Logic (CML) circuits. This new technique, with little overhead, using built-in detectors, monitor...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
In the reuse domain, the necessity of finding a new, more suitable description language opposes the need to make reuse an accepted practice, and thus related to standards. This pa...
DATE
1999
IEEE
14 years 1 months ago
1999
IEEE
Dynamically reconfigurable embedded systems offer potential for higher performance as well as adaptability to changing system requirements at low cost. Such systems employ run-tim...
ASPDAC
1999
ACM
14 years 1 months ago
1999
ACM
: This paper presents a method for evaluating an upper bound of simultaneous switching gates in combinational circuits. In this method, the original circuit is partitioned into sub...
ASPDAC
1999
ACM
14 years 1 months ago
1999
ACM
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring c...
ASPDAC
1999
ACM
14 years 1 months ago
1999
ACM
ASPDAC
1999
ACM
14 years 1 months ago
1999
ACM
In this paper we consider transistor sizing to reduce crosstalk. First, crosstalk noise dependency on wire width, wire spacing, driver and receiver sizes are discussed, and valida...
ASPDAC
1999
ACM
14 years 1 months ago
1999
ACM
This paper presents a performance-driven I/O pin routing algorithm with special consideration of wire uniformity. First, a topological routing based on min-cost max-flow algorith...
ASPDAC
1999
ACM
14 years 1 months ago
1999
ACM