We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced ...
M. Verhappen, P. H. A. van der Putten, Jeroen Voet...
A configurable memory organisation for the execution of Hiperlan/2 transceiver baseband processing and MPEG2 decoding is presented. The configuration of the memory system is done ...
Juha-Pekka Soininen, Antti Pelkonen, Jussi Roivain...
Modern microprocessors schedule instructions dynamically in order to exploit instruction-level parallelism. It is necessary to increase instruction window size for improving instr...
This paper1 addresses the hardware implementation of a dynamic scheduler for non-manifest data dependent periodic loops. Static scheduling techniques which are known to give near ...
In this paper, we propose an approach to the reduction of sizes of Multi-Terminal Binary Decision Diagrams (MTBDDs) [3] by using the copy properties of discrete functions. The und...
Dragan Jankovic, Radomir S. Stankovic, Rolf Drechs...
The Complex Streamed Instruction (CSI) set is an instruction set extension targeted at multimedia applications. CSI instructions process two-dimensional data streams stored in mem...
Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vass...
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
This paper presents a design for a low-power digital matched filter (DMF) applicable to Wideband-Code Division Multiple Access (W-CDMA), which is a Direct-Sequence Spread-Spectrum...
In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the po...