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DATE
2002
IEEE
77views Hardware» more  DATE 2002»
14 years 1 months ago
A Signature Test Framework for Rapid Production Testing of RF Circuits
Production test costs for today’s RF circuits are rapidly escalating. Two factors are responsible for this cost escalation: (a) the high cost of RF ATEs and (b) long test times ...
Ramakrishna Voorakaranam, Sasikumar Cherubal, Abhi...
DATE
2002
IEEE
90views Hardware» more  DATE 2002»
14 years 1 months ago
FPGA Placement by Thermodynamic Combinatorial Optimization
Juan de Vicente, Juan Lanchares, Román Herm...
DATE
2002
IEEE
79views Hardware» more  DATE 2002»
14 years 1 months ago
Incremental Diagnosis and Correction of Multiple Faults and Errors
An incremental simulation-based approach to fault diagnosis and logic debugging is presented. During each iteration of the algorithm, a single suspicious location is identified a...
Andreas G. Veneris, Jiang Brandon Liu, Mandana Ami...
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 1 months ago
FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis
This paper develops an improved approach for hierarchical functional test generation for complex chips. In order to deal with the increasing complexity of functional test generati...
Vivekananda M. Vedula, Jacob A. Abraham
DATE
2002
IEEE
101views Hardware» more  DATE 2002»
14 years 1 months ago
Systematic Design of a 200 Ms/S 8-bit Interpolating A/D Converter
The systematic design of a high-speed, high-accuracy Nyquist A/D converter is proposed. The presented design methodology covers the complete flow and is supported by software tool...
Jan Vandenbussche, Erik Lauwers, K. Uyttenhove, Mi...
DATE
2002
IEEE
124views Hardware» more  DATE 2002»
14 years 1 months ago
Crosstalk Alleviation for Dynamic PLAs
—The dynamic programmable logic array (PLA) style has become popular in designing high-performance microprocessors because of its high speed and predictable routing delay. Howeve...
Tzyy-Kuen Tien, Tong-Kai Tsai, Shih-Chieh Chang
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
14 years 1 months ago
Generalized Early Evaluation in Self-Timed Circuits
Phased logic has been proposed as a technique for realizing self-timed circuitry that is delay-insensitive and requires no global clock signals. Early evaluation techniques have b...
Mitchell A. Thornton, Kenneth Fazel, Robert B. Ree...
DATE
2002
IEEE
97views Hardware» more  DATE 2002»
14 years 1 months ago
Fast Method to Include Parasitic Coupling in Circuit Simulations
S-parameter based circuit simulators are used a lot for the design of microwave circuits. The accuracy of these simulators is limited by the fact that they do not take the electro...
B. L. A. Van Thielen, G. A. E. Vandenbosch
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 1 months ago
Improving Placement under the Constant Delay Model
In this paper, we show that under the constant delay model the placement problem is equivalent to minimizing a weighted sum of wire lengths. The weights can be efficiently compute...
Kolja Sulimma, Wolfgang Kunz, Ingmar Neumann, Luka...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 1 months ago
Macromodeling of Digital I/O Ports for System EMC Assessment
This paper addresses the development of accurate and efficient behavioral models of digital integrated circuit input and output ports for EMC and signal integrity simulations. A ...
Igor S. Stievano, Flavio G. Canavero, Ivan A. Maio...