DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. The...
DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
DSD
2002
IEEE
14 years 1 months ago
2002
IEEE
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
After the discussion on the difference between floorplanning and packing in VLSI placement design, this paper adapts the floorplanner that is based on the Q-sequence to a packin...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
Due to the increasing operating frequencies and the manner in which the corresponding integrated circuits and systems must be designed, the extraction, modeling and simulation of ...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
The design of application (-domain) specific instructionset processors (ASIPs), optimized for code size, has traditionally been accompanied by the necessity to program assembly, ...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
To enable fast and accurate evaluation of HW/SW implementation choices of on-chip communication, we present a method to automatically generate timed OS simulation models. The meth...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
In this paper, we study and implement a routabilitydriven floorplanner with buffer block planning. It evaluates the routability of a floorplan by computing the probability that ...
DATE
2002
IEEE
14 years 1 months ago
2002
IEEE
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...