Sciweavers

DATE
2002
IEEE
80views Hardware» more  DATE 2002»
14 years 1 months ago
Test Planning and Design Space Exploration in a Core-Based Environment
This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the considerati...
Érika F. Cota, Luigi Carro, Marcelo Lubasze...
DATE
2002
IEEE
87views Hardware» more  DATE 2002»
14 years 1 months ago
Model Reduction in the Time-Domain Using Laguerre Polynomials and Krylov Methods
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
Yiran Chen, Venkataramanan Balakrishnan, Cheng-Kok...
DATE
2002
IEEE
73views Hardware» more  DATE 2002»
14 years 1 months ago
A Burst-Mode Oriented Back-End for the Balsa Synthesis System
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley...
DATE
2002
IEEE
122views Hardware» more  DATE 2002»
14 years 1 months ago
Exploiting Idle Cycles for Algorithm Level Re-Computing
Although algorithm level re-computing techniques can trade-off the detection capability of Concurrent Error Detection (CED) vs. time overhead, it results in 100% time overhead whe...
Kaijie Wu, Ramesh Karri
DATE
2002
IEEE
103views Hardware» more  DATE 2002»
14 years 1 months ago
Test Resource Partitioning and Reduced Pin-Count Testing Based on Test Data Compression
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
Anshuman Chandra, Krishnendu Chakrabarty
DATE
2002
IEEE
131views Hardware» more  DATE 2002»
14 years 1 months ago
Passive Constrained Rational Approximation Algorithm Using Nevanlinna-Pick Interpolation
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. For high-spee...
Carlos P. Coelho, Luis Miguel Silveira, Joel R. Ph...
DATE
2002
IEEE
79views Hardware» more  DATE 2002»
14 years 1 months ago
Formulation of Low-Order Dominant Poles for Y-Matrix of Interconnects
This paper presents an efficient approach to compute the dominant poles for the reduced-order admittance (Y parameter) matrix of lossy interconnects. Using the global approximati...
Qinwei Xu, Pinaki Mazumder
DATE
2002
IEEE
126views Hardware» more  DATE 2002»
14 years 1 months ago
Automated Modeling of Custom Digital Circuits for Test
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
Soumitra Bose
DATE
2002
IEEE
141views Hardware» more  DATE 2002»
14 years 1 months ago
A Data Analysis Method for Software Performance Prediction
This paper explores the role of data analysis methods to support system-level designers in characterising the performance of embedded applications. In particular, we address the p...
Gianluca Bontempi, Wido Kruijtzer