This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the considerati...
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
This paper introduces several new component clustering techniques for the optimization of asynchronous systems. In particular, novel “Burst-Mode aware” restrictions are impose...
Tiberiu Chelcea, Steven M. Nowick, Andrew Bardsley...
Although algorithm level re-computing techniques can trade-off the detection capability of Concurrent Error Detection (CED) vs. time overhead, it results in 100% time overhead whe...
We present a new test resource partitioning (TRP) technique for reduced pin-count testing of system-on-a-chip (SOC). The proposed technique is based on test data compression and o...
As system integration evolves and tighter design constraints must be met, it becomes necessary to account for the non-ideal behavior of all the elements in a system. For high-spee...
Carlos P. Coelho, Luis Miguel Silveira, Joel R. Ph...
This paper presents an efficient approach to compute the dominant poles for the reduced-order admittance (Y parameter) matrix of lossy interconnects. Using the global approximati...
Models meant for logic verification and simulation are often used for ATPG. For custom digital circuits, these models contain many tristate devices, which leads to lower fault co...
This paper explores the role of data analysis methods to support system-level designers in characterising the performance of embedded applications. In particular, we address the p...