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DATE
2002
IEEE
156views Hardware» more  DATE 2002»
14 years 1 months ago
Dynamic VTH Scaling Scheme for Active Leakage Power Reduction
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
Chris H. Kim, Kaushik Roy
DATE
2002
IEEE
81views Hardware» more  DATE 2002»
14 years 1 months ago
A Two-Tier Distributed Electronic Design Framework
Tom J. Kazmierski, Neil Clayton
DATE
2002
IEEE
104views Hardware» more  DATE 2002»
14 years 1 months ago
A Compiler-Based Approach for Improving Intra-Iteration Data Reuse
Intra-iteration data reuse occurs when multiple array references exhibit data reuse in a single loop iteration. An optimizing compiler can exploit this reuse by clustering (in the...
Mahmut T. Kandemir
DATE
2002
IEEE
101views Hardware» more  DATE 2002»
14 years 1 months ago
EAC: A Compiler Framework for High-Level Energy Estimation and Optimization
This paper presents a novel Energy-Aware Compilation (EAC) framework that can estimate and optimize energy consumption of a given code taking as input the architectural and techno...
Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vija...
DATE
2002
IEEE
95views Hardware» more  DATE 2002»
14 years 1 months ago
A Polynomial Time Optimal Diode Insertion/Routing Algorithm for Fixing Antenna Problem
Abstract—Antenna problem is a phenomenon of plasma-induced gateoxide degradation. It directly affects manufacturability of very large scale integration (VLSI) circuits, especiall...
Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong,...
DATE
2002
IEEE
74views Hardware» more  DATE 2002»
14 years 1 months ago
Maze Routing with Buffer Insertion under Transition Time Constraints
In this paper, we address the problem of simultaneous routing and buffer insertion. Recently in [12, 22], the authors considered simultaneous maze routing and buffer insertion und...
Li-Da Huang, Minghorng Lai, D. F. Wong, Youxin Gao
DATE
2002
IEEE
84views Hardware» more  DATE 2002»
14 years 1 months ago
Performance-Area Trade-Off of Address Generators for Address Decoder-Decoupled Memory
Multimedia applications are characterized by a large number of data accesses and complex array index manipulations. The built-in address decoder in the RAM memory model commonly u...
Sambuddhi Hettiaratchi, Peter Y. K. Cheung, Thomas...
DATE
2002
IEEE
75views Hardware» more  DATE 2002»
14 years 1 months ago
System Design for Flexibility
With the term flexibility, we introduce a new design dimension of an embedded system that quantitatively characterizes its feasibility in implementing not only one, but possibly ...
Christian Haubelt, Jürgen Teich, Kai Richter,...
DATE
2002
IEEE
69views Hardware» more  DATE 2002»
14 years 1 months ago
Verifying Clock Schedules in the Presence of Cross Talk
This paper addresses verifying the timing of circuits containing level-sensitive latches in the presence of cross talk. We show that three consecutive periodic occurrences of the ...
Soha Hassoun, Eduardo Calvillo-Gámez, Chris...