Sciweavers

DATE
2002
IEEE
82views Hardware» more  DATE 2002»
14 years 1 months ago
Dynamic Scheduling and Clustering in Symbolic Image Computation
The core computation in BDD-based symbolic synthesis and verification is forming the image and pre-image of sets of states under the transition relation characterizing the sequen...
Gianpiero Cabodi, Paolo Camurati, Stefano Quer
DATE
2002
IEEE
94views Hardware» more  DATE 2002»
14 years 1 months ago
A Powerful System Design Methodology Combining OCAPI and Handel-C for Concept Engineering
In this paper, we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict topdown Hardware/So...
Klaus Buchenrieder, Andreas Pyttel, Alexander Sedl...
DATE
2002
IEEE
154views Hardware» more  DATE 2002»
14 years 1 months ago
Low Power Error Resilient Encoding for On-Chip Data Buses
As technology scales toward deep submicron, on-chip interconnects are becoming more and more sensitive to noise sources such as power supply noise, crosstalk, radiation induced ef...
Davide Bertozzi, Luca Benini, Giovanni De Micheli
DATE
2002
IEEE
102views Hardware» more  DATE 2002»
14 years 1 months ago
New Techniques for Speeding-Up Fault-Injection Campaigns
Luis Berrojo, Isabel González, Fulvio Corno...
DATE
2002
IEEE
111views Hardware» more  DATE 2002»
14 years 1 months ago
A Linear-Centric Modeling Approach to Harmonic Balance Analysis
In this paper we propose a new harmonic balance simulation methodology based on a linear-centric modeling approach. A linear circuit representation of the nonlinear devices and as...
Peng Li, Lawrence T. Pileggi
DATE
2002
IEEE
77views Hardware» more  DATE 2002»
14 years 1 months ago
An Optimal Algorithm for the Automatic Generation of March Tests
This paper presents an innovative algorithm for the automatic generation of March Tests. The proposed approach is able to generate an optimal March Test for an unconstrained set o...
Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale...
DATE
2002
IEEE
99views Hardware» more  DATE 2002»
14 years 1 months ago
Gate Level Fault Diagnosis in Scan-Based BIST
A gate level, automated fault diagnosis scheme is proposed for scan-based BIST designs. The proposed scheme utilizes both fault capturing scan chain information and failing test v...
Ismet Bayraktaroglu, Alex Orailoglu
DATE
2002
IEEE
96views Hardware» more  DATE 2002»
14 years 1 months ago
Modeling Techniques and Tests for Partial Faults in Memory Devices
: It has always been assumed that fault models in memories are sufficiently precise for specifying the faulty behavior. This means that, given a fault model, it should be possible...
Zaid Al-Ars, A. J. van de Goor
DATE
2002
IEEE
136views Hardware» more  DATE 2002»
14 years 1 months ago
Beyond UML to an End-of-Line Functional Test Engine
In this paper, we analyze the use of UML as a starting point to go from design issues to end of production testing of complex embedded systems. The first point is the analysis of ...
Andrea Baldini, Alfredo Benso, Paolo Prinetto, Ser...
DATE
2002
IEEE
96views Hardware» more  DATE 2002»
14 years 1 months ago
A Linear-Centric Simulation Framework for Parametric Fluctuations
The relative tolerances for interconnect and device parameter variations have not scaled with feature sizes which have brought about significant performance variability. As we sca...
Emrah Acar, Sani R. Nassif, Lawrence T. Pileggi