ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
In this paper we propose a new design methodology targeted for core-based designs using parameterized macrocells (PMC’s). This methodology provides the flexibility for instance...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
A structurally testable delay fault might become untestable in the functional mode of the circuit due to logic or timing constraints or both. Experimental data suggests that there...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
We present a new technique for generating compact dictionaries for cause-effect diagnosis in BIST. This approach relies on the use of three compact dictionaries: (i) D1, containin...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-Â...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
This paper proposes a new clocking strategy for dynamic circuit. It provides faster performance and smaller area than conventional clocking scheme. The proposed clocking scheme fo...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
Mind-boggling complexity of EDA tools necessitates reuse of intellectual property in any large-scale commercial or academic operation. However, due to the nature of software, a to...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
Approach Abstracts AltPSM Lithography Requirements for sub-100nm IC Design Domains Pradiptya Ghosh, Chung-shin Kang, Michael Sanie and David Pinto Numerical Technologies, 70 West P...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
ISQED
2003
IEEE
14 years 2 months ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...