125
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
This paper presents an approach for analysis of system state differences observable through the scan chain for the debug of functional failures. A novel methodology for Latch Dive...
113
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
This work discusses the impact of power consumption on the test time of core-based systems, when an available on-chip network is reused as test access mechanism. A previously prop...
127
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
The interconnection network consumes the majority of die area in an FPGA. Presented is a scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple inter...
121
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
ct This paper describes a general technique to test external memory/caches and memory interconnects using on-chip logic. Such a test methodology is expected to significantly reduc...
150
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
Scan-based architectures, though widely used in modern designs, are expensive in power consumption. In this paper, we present a new technique that allows to design power-optimized...
136
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
Multiple-detect test sets have been shown to be effective in lowering defect level. Other researchers have noted that observing the effects of a defect can be controlled by sensit...
154
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
In a scan-based system with a large number of flip-flops, a major component of power is consumed during scanshift and clocking operation in test mode. In this paper, a novel scan-...
102
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizi...
113
click to vote
ITC
2003
IEEE
15 years 10 months ago
2003
IEEE
An early-life reliability model is presented that allows wafer test information to be used to predict not only the total number of burn-in failures that occur for a given product,...