Sciweavers

ISQED
2003
IEEE
134views Hardware» more  ISQED 2003»
14 years 2 months ago
Concurrent Fault Detection in Random Combinational Logic
We discuss a non-intrusive methodology for concurrent fault detection in random combinational logic. The proposed method is similar to duplication, wherein a replica of the circui...
Petros Drineas, Yiorgos Makris
ISQED
2003
IEEE
71views Hardware» more  ISQED 2003»
14 years 2 months ago
A Proposal for Routing-Based Timing-Driven Scan Chain Ordering
Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wireleng...
Puneet Gupta, Andrew B. Kahng, Stefanus Mantik
ISQED
2003
IEEE
85views Hardware» more  ISQED 2003»
14 years 2 months ago
Interoperability Beyond Design: Sharing Knowledge between Design and Manufacturing
The nature of IC design has is necessarily evolving to a more data-centric design flow in which EDA tools share a common information in a design database without the negative cost...
D. R. Cottrell, T. J. Grebinski
ISQED
2003
IEEE
104views Hardware» more  ISQED 2003»
14 years 2 months ago
Comparative Assessment of Adaptive Body-Bias SOI Pass-Transistor Logic
We present a silicon-on-insulator (SOI) pass-transistor logic (PTL) gate with an active body bias control circuit and compare the proposed PTL gate with other types of PTL gates w...
Geun Rae Cho, Tom Chen
ISQED
2003
IEEE
109views Hardware» more  ISQED 2003»
14 years 2 months ago
Modeling and Analysis of Power Distribution Networks for Gigabit Applications
—As the operating frequency of digital systems increases and voltage swing decreases, it becomes very important to characterize and analyze power distribution networks (PDNs) acc...
Wendemagegnehu T. Beyene, Chuck Yuan, Joong-Ho Kim...
ISQED
2003
IEEE
116views Hardware» more  ISQED 2003»
14 years 2 months ago
Analyzing Statistical Timing Behavior of Coupled Interconnects Using Quadratic Delay Change Characteristics
With continuing scaling of CMOS process, process variations in the form of die-to-die and within-die variations become significant which cause timing uncertainty. This paper prop...
Tom Chen, Amjad Hajjar
ISQED
2003
IEEE
113views Hardware» more  ISQED 2003»
14 years 2 months ago
Using Integer Equations for High Level Formal Verification Property Checking
This paper describes the use of integer equations for high level modeling digital circuits for application of formal verification properties at this level. Most formal verificatio...
Bijan Alizadeh, Mohammad Reza Kakoee
ISQED
2003
IEEE
215views Hardware» more  ISQED 2003»
14 years 2 months ago
Low-Cost and Real-Time Super-Resolution over a Video Encoder IP
This paper addresses a low-cost and real-time solution for the implementation of super-resolution (SR) algorithms over SOC (System-On-Chip) platforms in order to achieve high-qual...
Gustavo Marrero Callicó, Antonio Nú&...
ISQED
2003
IEEE
60views Hardware» more  ISQED 2003»
14 years 2 months ago
Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains
Afshin Abdollahi, Farzan Fallah, Massoud Pedram