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ITC
2003
IEEE
148views Hardware» more  ITC 2003»
14 years 2 months ago
HyAC: A Hybrid Structural SAT Based ATPG for Crosstalk
As technology evolves into the deep sub-micron era, signal integrity problems are growing into a major challenge. An important source of signal integrity problems is the crosstalk...
Xiaoliang Bai, Sujit Dey, Angela Krstic
ITC
2003
IEEE
123views Hardware» more  ITC 2003»
14 years 2 months ago
Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores
1 This paper addresses the issue of testing and diagnosing a memory core embedded in a complex SOC. The proposed solution is based on a P1500-compliant wrapper that follows a progr...
Davide Appello, Paolo Bernardi, Alessandra Fudoli,...
ITC
2003
IEEE
151views Hardware» more  ITC 2003»
14 years 2 months ago
Fault Collapsing via Functional Dominance
A fault fj is said to dominate another fault fi if all tests for fi detect fj . When two faults dominate each other, they are called equivalent. Dominance and equivalence relation...
Vishwani D. Agrawal, A. V. S. S. Prasad, Madhusuda...
ITC
2003
IEEE
145views Hardware» more  ITC 2003»
14 years 2 months ago
CHARDIN: An Off-Chip Transient Current Monitor with Digital Interface for Production Testing
We present a measurement module that computes the charge from the transient supply current and provides a digital value of this magnitude. The module is constructed to provide a f...
Bartomeu Alorda, B. Bloechel, Ali Keshavarzi, Jaum...
ISQED
2003
IEEE
86views Hardware» more  ISQED 2003»
14 years 2 months ago
Electrical and Thermal Analysis for System-in-a-Package (SiP) Implementation Platform
This paper presents an electrical and thermal performance analysis of System-in-a-Package (SiP) memory/logic implementation platform based on ChipLaminate-Chip (CLC) technology. I...
Michael X. Wang, Katsuharu Suzuki, Wayne Wei-Ming ...
ISQED
2003
IEEE
133views Hardware» more  ISQED 2003»
14 years 2 months ago
Impact of Interconnect Pattern Density Information on a 90nm Technology ASIC Design Flow
The importance of an interconnect pattern density model in ASIC design flow for a 90nm technology is presented. It is shown that performing the timing analysis at the worst-case c...
Payman Zarkesh-Ha, S. Lakshminarayann, Ken Doniger...
ISQED
2003
IEEE
78views Hardware» more  ISQED 2003»
14 years 2 months ago
An Embedded IDDQ Testing Architecture and Technique
In this paper an embedded IDDQ testing architecture is presented that targets to overcome the excessive hardware overhead requirements in built-in current sensing based testing ap...
Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni
ISQED
2003
IEEE
102views Hardware» more  ISQED 2003»
14 years 2 months ago
Modeling Crosstalk Induced Delay
The amplitude of coupled noise is often used in estimating the crosstalk effect. Coupling noise-induced delay measures the impact of crosstalk on circuit performance. Efficient c...
Chung-Kuan Tsai, Malgorzata Marek-Sadowska
ISQED
2003
IEEE
133views Hardware» more  ISQED 2003»
14 years 2 months ago
Analyzing Internal-Switching Induced Simultaneous Switching Noise
The internal-switching induced simultaneous switching noise (SSN) is studied in the paper. Unlike ground bounce caused by driving off-chip loading, both power-rail and ground-rail...
Li Yang, J. S. Yuan
ISQED
2003
IEEE
104views Hardware» more  ISQED 2003»
14 years 2 months ago
Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis
As the portion of coupling capacitance increases in smaller process geometries, accurate coupled noise analysis is becoming more important in current design methodologies. We prop...
Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-...