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ICCAD
2009
IEEE
117views Hardware» more  ICCAD 2009»
13 years 5 months ago
Binning optimization based on SSTA for transparently-latched circuits
With increasing process variation, binning has become an important technique to improve the values of fabricated chips, especially in high performance microprocessors where transpa...
Min Gong, Hai Zhou, Jun Tao, Xuan Zeng
FPL
2009
Springer
103views Hardware» more  FPL 2009»
13 years 5 months ago
Customizable domain-specific computing
In this article, we introduce the ongoing research in modeling and mapping for heterogeneous, customizable, parallel systems, as part of the effort in the newly established Center...
Jason Cong
FIC
2009
97views Hardware» more  FIC 2009»
13 years 5 months ago
Vers une ontologie formelle des artefacts
ts niveaux d'abstraction. Sch
Gilles Kassel
FIC
2009
85views Hardware» more  FIC 2009»
13 years 5 months ago
Indexation de photos sociales par propagation sur une hiérarchie de concepts
Michel Crampes, Jeremy de Oliveira-Kumar, Sylvie R...
EUROCAST
2009
Springer
153views Hardware» more  EUROCAST 2009»
13 years 5 months ago
Algorithm for Testing the Leibniz Algebra Structure
Abstract. Given a basis of a vector space V over a field K and a multiplication table which defines a bilinear map on V , we develop a computer program on Mathematica which checks ...
José Manuel Casas, Manuel A. Insua, Manuel ...
ETS
2009
IEEE
128views Hardware» more  ETS 2009»
13 years 5 months ago
Algorithms for ADC Multi-site Test with Digital Input Stimulus
This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both ...
Xiaoqin Sheng, Hans G. Kerkhoff, Amir Zjajo, Guido...
ETS
2009
IEEE
98views Hardware» more  ETS 2009»
13 years 5 months ago
Increasing Robustness of SAT-based Delay Test Generation Using Efficient Dynamic Learning Techniques
Due to the increased speed in modern designs, testing for delay faults has become an important issue in the postproduction test of manufactured chips. A high fault coverage is nee...
Stephan Eggersglüß, Rolf Drechsler
ETS
2009
IEEE
117views Hardware» more  ETS 2009»
13 years 5 months ago
A Two Phase Approach for Minimal Diagnostic Test Set Generation
We optimize the full-response diagnostic fault dictionary from a given test set. The smallest set of vectors is selected without loss of diagnostic resolution of the given test se...
Mohammed Ashfaq Shukoor, Vishwani D. Agrawal
ETS
2009
IEEE
99views Hardware» more  ETS 2009»
13 years 5 months ago
On Minimization of Peak Power for Scan Circuit during Test
Scan circuit generally causes excessive switching activity compared to normal circuit operation. The higher switching activity in turn causes higher peak power supply current whic...
Jaynarayan T. Tudu, Erik Larsson, Virendra Singh, ...