It has been shown that many requests miss in all remote nodes in shared memory multiprocessors. We are motivated by the observation that this behavior extends to much coarser grai...
This paper presents a hardware-based dynamic optimizer that continuously optimizes an application’s instruction stream. In continuous optimization, dataflow optimizations are p...
Brian Fahs, Todd M. Rafacz, Sanjay J. Patel, Steve...
We propose “secret-protected (SP)” architecture to enable secure and convenient protection of critical secrets for a given user in an on-line environment. Keys are examples of...
Ruby B. Lee, Peter C. S. Kwan, John Patrick McGreg...
Lossless data compression techniques can potentially free up more than 50% of the memory resources. However, previously proposed schemes suffer from high access costs. The propose...
This paper examines the area, power, performance, and design issues for the on-chip interconnects on a chip multiprocessor, attempting to present a comprehensive view of a class o...
Evolving semiconductor and circuit technology has greatly increased the pin bandwidth available to a router chip. In the early 90s, routers were limited to 10Gb/s of pin bandwidth...
John Kim, William J. Dally, Brian Towles, Amit K. ...
Improved branch prediction accuracy is essential to sustaining instruction throughput with today’s deep pipelines. We introduce piecewise linear branch prediction, an idealized ...
Recent I/O technologies such as PCI-Express and 10Gb Ethernet enable unprecedented levels of I/O bandwidths in mainstream platforms. However, in traditional architectures, memory ...
Recent years have seen a burgeoning interest in embedded wireless sensor networks with applications ranging from habitat monitoring to medical applications. Wireless sensor networ...
Mark Hempstead, Nikhil Tripathi, Patrick Mauro, Gu...