Sciweavers

ISQED
2005
IEEE
98views Hardware» more  ISQED 2005»
14 years 2 months ago
A More Effective CEFF
Precise chip-level timing requires careful modeling of the interaction between logic drivers and interconnect. Existing static-timing analysis methodologies generate models for dr...
Sani R. Nassif, Zhuo Li
ISQED
2005
IEEE
81views Hardware» more  ISQED 2005»
14 years 2 months ago
Welcome Notes
ISQED
2005
IEEE
64views Hardware» more  ISQED 2005»
14 years 2 months ago
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET
Double-Gate (DG) transistor has emerged as the most promising device for nano-scale circuit design. Independent control of front and back gate in DG devices can be effectively use...
Saibal Mukhopadhyay, Hamid Mahmoodi-Meimand, Kaush...
ISQED
2005
IEEE
120views Hardware» more  ISQED 2005»
14 years 2 months ago
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
This paper presents a novel compact passive modeling technique for high-performance RF passives and interconnects modeled as high-order RLCM circuits. The new method is based on a...
Pu Liu, Zhenyu Qi, Sheldon X.-D. Tan
ISQED
2005
IEEE
92views Hardware» more  ISQED 2005»
14 years 2 months ago
Evaluation of Capacitor Ratios in Automated Accurate Common-Centroid Capacitor Arrays
In this paper, design and measurement results of a test chip that intends to evaluate differences between layout techniques for rectangular unit-capacitor arrays are introduced. P...
DiaaEldin Khalil, Mohamed Dessouky, Vincent Bourgu...
ISQED
2005
IEEE
95views Hardware» more  ISQED 2005»
14 years 2 months ago
Simulating and Improving Microelectronic Device Reliability by Scaling Voltage and Temperature
The purpose of this work is to explore how device operation parameters such as switching speed and power dissipation scale with voltage and temperature. We simulated a CMOS ring o...
Xiaojun Li, Joerg D. Walter, Joseph B. Bernstein
ISQED
2005
IEEE
106views Hardware» more  ISQED 2005»
14 years 2 months ago
Deep Submicron CMOS Integrated Circuit Reliability Simulation with SPICE
The purpose of the paper is to introduce a new failure rate-based methodology for reliability simulation of deep submicron CMOS integrated circuits. Firstly, two of the state-of-t...
Xiaojun Li, Bing Huang, J. Qin, X. Zhang, Michael ...
ISQED
2005
IEEE
95views Hardware» more  ISQED 2005»
14 years 2 months ago
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis
As technology scales down, power supply noise is becoming a performance and reliability bottleneck in modern VLSI. We propose a power supply noise-aware design methodology for hig...
Dongku Kang, Yiran Chen, Kaushik Roy
ISQED
2005
IEEE
169views Hardware» more  ISQED 2005»
14 years 2 months ago
ASLIC: A Low Power CMOS Analog Circuit Design Automation
This paper proposes an efficient automation platform that provides fast and reliable path to analog circuit design for desired specifications. Circuit heuristics and hierarchy a...
Jihyun Lee, Yong-Bin Kim
ISQED
2005
IEEE
76views Hardware» more  ISQED 2005»
14 years 2 months ago
Reticle Floorplanning and Wafer Dicing for Multiple Project Wafers
Multi-project wafer having several chips placed on the same reticle to lower mask cost is key to low-volume IC fabrication. In this paper1 , we proposed two MILP models for simult...
Meng-Chiou Wu, Rung-Bin Lin