Sciweavers

FPT
2005
IEEE
134views Hardware» more  FPT 2005»
14 years 2 months ago
Post-Silicon Debug Using Programmable Logic Cores
Producing a functionally correct integrated circuit is becoming increasingly difficult. No matter how careful a designer is, there will always be integrated circuits that are fabr...
Bradley R. Quinton, Steven J. E. Wilton
FPT
2005
IEEE
127views Hardware» more  FPT 2005»
14 years 2 months ago
Pipelining Saturated Accumulation
Aggressive pipelining allows FPGAs to achieve high throughput on many Digital Signal Processing applications. However, cyclic data dependencies in the computation can limit pipeli...
Karl Papadantonakis, Nachiket Kapre, Stephanie Cha...
FPT
2005
IEEE
198views Hardware» more  FPT 2005»
14 years 2 months ago
From TLM to FPGA: Rapid Prototyping with SystemC and Transaction Level Modeling
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
Wolfgang Klingauf, Robert Günzel
FPT
2005
IEEE
133views Hardware» more  FPT 2005»
14 years 2 months ago
FPGA-Based Conformance Testing and System Prototyping of an MPEG-4 SA-DCT Hardware Accelerator
Two FPGA implementations of a Shape Adaptive Discrete Cosine Transform (SA-DCT) accelerator are presented in this paper: one PCI-based and the other AMBA-based. The former is used...
Andrew Kinane, Alan Casey, Valentin Muresan, Noel ...
FPT
2005
IEEE
142views Hardware» more  FPT 2005»
14 years 2 months ago
Custom Hardware Architectures for Posture Analysis
This paper describes the design and implementation of hardware architectures for posture analysis. Posture analysis is an active research area in computer vision. It can be used i...
M. P. T. Juvonen, José Gabriel F. Coutinho,...
FPT
2005
IEEE
125views Hardware» more  FPT 2005»
14 years 2 months ago
An Adaptive Cryptographic Accelerator for IPsec on Dynamically Reconfigurable Processor
Yohei Hasegawa, Shohei Abe, Hiroki Matsutani, Hide...
FPT
2005
IEEE
181views Hardware» more  FPT 2005»
14 years 2 months ago
Hardware-Accelerated SSH on Self-Reconfigurable Systems
The performance of security applications can be greatly improved by accelerating the cryptographic algorithms in hardware. In this paper, an implementation of the Secure Shell (SS...
Ivan Gonzalez, Francisco J. Gomez-Arribas, Sergio ...
FPT
2005
IEEE
98views Hardware» more  FPT 2005»
14 years 2 months ago
Secure Partial Reconfiguration of FPGAs
SRAM FPGAs are vulnerable to security breaches such as bitstream cloning, reverse-engineering, and tampering. Bitstream encryption and authentication are two most effective and pr...
Amir Sheikh Zeineddini, Kris Gaj
FPT
2005
IEEE
131views Hardware» more  FPT 2005»
14 years 2 months ago
Dynamic Voltage Scaling for Commercial FPGAs
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, ...
FPT
2005
IEEE
132views Hardware» more  FPT 2005»
14 years 2 months ago
Implementation of Gabor-Type Filters on Field Programmable Gate Arrays
Although biological visual systems have been widely studied at the physiological, psychophysical and functional levels, our understanding of its signal processing mechanisms is st...
Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K....