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ATS
2005
IEEE
98views Hardware» more  ATS 2005»
14 years 2 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
ATS
2005
IEEE
100views Hardware» more  ATS 2005»
14 years 2 months ago
A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects
In this paper, we present a methodology that uses the moments of a generic crosstalk pulse signal to derive upper bounds on the amplitude of crosstalk pulse in arbitrary interconn...
Wichian Sirisaengtaksin, Sandeep K. Gupta
ATS
2005
IEEE
104views Hardware» more  ATS 2005»
14 years 2 months ago
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM
In this paper, we develop a method to analyze the probability of access failure in SRAM array (due to random Vt variation in transistors) by jointly considering variations in cell...
Saibal Mukhopadhyay, Arijit Raychowdhury, Hamid Ma...
ATS
2005
IEEE
84views Hardware» more  ATS 2005»
14 years 2 months ago
Current Testing for Nanotechnologies: A Demystifying Application Perspective.
: This paper addresses the challenges imposed on current testing with the advent of Nanotechnologies. It shows why existing measurement solutions embedded in ATE systems are not ad...
Hans A. R. Manhaeve
ATS
2005
IEEE
100views Hardware» more  ATS 2005»
14 years 2 months ago
Finite State Machine Synthesis for At-Speed Oscillation Testability
In this paper, we propose an oscillation-based test methodology for sequential testing. This approach provides many advantages over traditional methods. (1) It is at-speed testing...
Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, ...
ATS
2005
IEEE
91views Hardware» more  ATS 2005»
14 years 2 months ago
SOC Test Scheduling with Test Set Sharing and Broadcasting
11 Due to the increasing test data volume needed to test corebased System-on-Chip, several test scheduling techniques minimizing the test application time have been proposed. In co...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ATS
2005
IEEE
144views Hardware» more  ATS 2005»
14 years 2 months ago
On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
—Test application at reduced power supply voltage (low-voltage testing) or reduced temperature (low-temperature testing) can improve the defect coverage of a test set, particular...
Sandip Kundu, Piet Engelke, Ilia Polian, Bernd Bec...
ATS
2005
IEEE
139views Hardware» more  ATS 2005»
14 years 2 months ago
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability
— Structural transformation of a design to enhance its testability while satisfying design constraints on power and performance, can result in improved test cost and test confid...
Swaroop Ghosh, Swarup Bhunia, Kaushik Roy
ATS
2005
IEEE
118views Hardware» more  ATS 2005»
14 years 2 months ago
Partial Gating Optimization for Power Reduction During Test Application
Power reduction during test application is important from the viewpoint of chip reliability and for obtaining correct test results. One of the ways to reduce scan test power is to...
Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ra...
ATS
2005
IEEE
80views Hardware» more  ATS 2005»
14 years 2 months ago
A Class of Linear Space Compactors for Enhanced Diagnostic
Thomas Clouqueur, Hideo Fujiwara, Kewal K. Saluja