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ATS
2005
IEEE
121views Hardware» more  ATS 2005»
14 years 2 months ago
Compressing Functional Tests for Microprocessors
In the past, test data volume reduction techniques have concentrated heavily on scan test data content. However, functional vectors continue to be utilized because they target uni...
Kedarnath J. Balakrishnan, Nur A. Touba, Srinivas ...
ATS
2005
IEEE
56views Hardware» more  ATS 2005»
14 years 2 months ago
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach
Abstract: Fabrication process improvements and technology scaling results in modifications in the characteristics and in the behavior of manufactured memory chips, which also modi...
Zaid Al-Ars, Said Hamdioui, Jörg E. Vollrath
ATS
2005
IEEE
132views Hardware» more  ATS 2005»
14 years 2 months ago
Concurrent Test Generation
We define a new type of test, called “concurrent test,” for a combinational circuit. Given a set of target faults, a concurrent-test is an input vector that detects all (or m...
Vishwani D. Agrawal, Alok S. Doshi
ASYNC
2005
IEEE
132views Hardware» more  ASYNC 2005»
14 years 2 months ago
High Level Synthesis of Timed Asynchronous Circuits
This paper proposes applying a logic synthesis approach to high level synthesis from SpecC specifications to timed asynchronous gate-level circuits. The state-based logic synthes...
Tomohiro Yoneda, Atsushi Matsumoto, Manabu Kato, C...
ASYNC
2005
IEEE
174views Hardware» more  ASYNC 2005»
14 years 2 months ago
Delay Insensitive Encoding and Power Analysis: A Balancing Act
Unprotected cryptographic hardware is vulnerable to a side-channel attack known as Differential Power Analysis (DPA). This attack exploits data-dependent power consumption of a co...
Konrad J. Kulikowski, Ming Su, Alexander B. Smirno...
ASYNC
2005
IEEE
118views Hardware» more  ASYNC 2005»
14 years 2 months ago
Modeling and Verifying Circuits Using Generalized Relative Timing
We propose a novel technique for modeling and verifying timed circuits based on the notion of generalized relative timing. Generalized relative timing constraints can express not ...
Sanjit A. Seshia, Randal E. Bryant, Kenneth S. Ste...
ASYNC
2005
IEEE
96views Hardware» more  ASYNC 2005»
14 years 2 months ago
GasP Control for Domino Circuits
We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare...
Jo C. Ebergen, Jonathan Gainsley, Jon K. Lexau, Iv...
ASYNC
2005
IEEE
71views Hardware» more  ASYNC 2005»
14 years 2 months ago
Proximity Communication and Time
Robert J. Drost, Ivan E. Sutherland
ASYNC
2005
IEEE
97views Hardware» more  ASYNC 2005»
14 years 2 months ago
Self-Timed Circuitry for Global Clocking
We present an apparatus used to distribute a timing reference or clock across the extent of a digital system. Selftimed circuitry both generates and distributes a clock signal, wh...
Scott Fairbanks, Simon W. Moore
ASYNC
2005
IEEE
90views Hardware» more  ASYNC 2005»
14 years 2 months ago
SEU-Tolerant QDI Circuits
This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circu...
Wonjin Jang, Alain J. Martin