Sciweavers

DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 3 months ago
A built-in redundancy-analysis scheme for RAMs with 2D redundancy using 1D local bitmap
Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-onchips (SOCs). To increase the utilization of memory redundancy, the BISR t...
Tsu-Wei Tseng, Jin-Fu Li, Da-Ming Chang
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
14 years 3 months ago
Value-based bit ordering for energy optimization of on-chip global signal buses
In this paper, we present a technique that exploits the statistical behavior of data values transmitted on global signal buses to determine an energy-efficient ordering of bits t...
Krishnan Sundaresan, Nihar R. Mahapatra
DATE
2006
IEEE
142views Hardware» more  DATE 2006»
14 years 3 months ago
Droplet routing in the synthesis of digital microfluidic biochips
same level of system-level CAD support that is now commonplace in the IC industry.Recent advances in microfluidics are expected to lead to sensor systems for high-throughput bioche...
Fei Su, William L. Hwang, Krishnendu Chakrabarty
DATE
2006
IEEE
123views Hardware» more  DATE 2006»
14 years 3 months ago
Networks on chips for high-end consumer-electronics TV system architectures
Consumer electronics products, such as high-end (digital) TVs, contain complex systems on chip (SOC) that offer high computational performance at low cost. Traditionally, these SO...
Frits Steenhof, Harry Duque, Björn Nilsson, K...
DATE
2006
IEEE
116views Hardware» more  DATE 2006»
14 years 3 months ago
Adaptive data placement in an embedded multiprocessor thread library
— Embedded multiprocessors pose new challenges in the design and implementation of embedded software. This has led to the need for programming interfaces that expose the capabili...
Phillip Stanley-Marbell, Kanishka Lahiri, Anand Ra...
DATE
2006
IEEE
158views Hardware» more  DATE 2006»
14 years 3 months ago
Modeling multiple input switching of CMOS gates in DSM technology using HDMR
Abstract— Continuing scaling of CMOS technology has allowed aggressive pursuant of increased clock rate in DSM chips. The ever shorter clock period has made switching times of di...
Jayashree Sridharan, Tom Chen
DATE
2006
IEEE
104views Hardware» more  DATE 2006»
14 years 3 months ago
Optimizing sequential cycles through Shannon decomposition and retiming
—Optimizing sequential cycles is essential for many types of high-performance circuits, such as pipelines for packet processing. Retiming is a powerful technique for speeding pip...
Cristian Soviani, Olivier Tardieu, Stephen A. Edwa...