Sciweavers

DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 3 months ago
How OEMs and suppliers can face the network integration challenges
Systems integration is a major challenge in many industries. Systematic analysis of the complex integration effects, especially with respect to timing and performance, significant...
Kai Richter, Rolf Ernst
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
14 years 3 months ago
Sociology of design and EDA
Walden C. Rhines
DATE
2006
IEEE
153views Hardware» more  DATE 2006»
14 years 3 months ago
Analyzing timing uncertainty in mesh-based clock architectures
Mesh architectures are used to distribute critical global signals on a chip, such as clock and power/ground. Redundancy created by mesh loops smooths out undesirable variations be...
Subodh M. Reddy, Gustavo R. Wilke, Rajeev Murgai
DATE
2006
IEEE
114views Hardware» more  DATE 2006»
14 years 3 months ago
An efficient static algorithm for computing the soft error rates of combinational circuits
Soft errors have emerged as an important reliability challenge for nanoscale VLSI designs. In this paper, we present a fast and efficient soft error rate (SER) computation algorit...
Rajeev R. Rao, Kaviraj Chopra, David Blaauw, Denni...
DATE
2006
IEEE
159views Hardware» more  DATE 2006»
14 years 3 months ago
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors
Reduced energy consumption is one of the most important design goals for embedded application domains like wireless, multimedia and biomedical. Instruction memory hierarchy has be...
Praveen Raghavan, Andy Lambrechts, Murali Jayapala...
DATE
2006
IEEE
91views Hardware» more  DATE 2006»
14 years 3 months ago
Customization of application specific heterogeneous multi-pipeline processors
Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswar...
DATE
2006
IEEE
92views Hardware» more  DATE 2006»
14 years 3 months ago
Space-efficient FPGA-accelerated collision detection for virtual prototyping
Andreas Raabe, Stefan Hochgürtel, Joachim K. ...
DATE
2006
IEEE
101views Hardware» more  DATE 2006»
14 years 3 months ago
A parallel configuration model for reducing the run-time reconfiguration overhead
Multitasking on reconfigurable logic can achieve very high silicon reusability. However, configuration latency is a major limitation and it can largely degrade the system performa...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
DATE
2006
IEEE
105views Hardware» more  DATE 2006»
14 years 3 months ago
Comfortable modeling of complex reactive systems
Modeling systems based on semi-formal graphical formalisms, such as Statecharts, has become standard practice in the design of reactive embedded devices. However, the modeling of ...
Steffen Prochnow, Reinhard von Hanxleden
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 3 months ago
Test compaction for transition faults under transparent-scan
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
Irith Pomeranz, Sudhakar M. Reddy