Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures ha...
This paper addresses an XML-based design environment, which provides a powerful basis for the manipulation of hardware design descriptions. The contribution of the paper is a flex...
Jan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Ros...
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis A...
We report the first fully integrated single photon avalanche diode array fabricated in 0.35µm CMOS technology. At 25µm, the pixel pitch achieved by this design is the smallest e...
Cristiano Niclass, Maximilian Sergio, Edoardo Char...
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used t...
Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jas...
In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources i...
Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Su...
This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, ex...
Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta,...
Abstract - A cell delay model based on rate-of-currentchange is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More pre...
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...