Sciweavers

DATE
2006
IEEE
149views Hardware» more  DATE 2006»
14 years 3 months ago
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures ha...
Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee...
DATE
2006
IEEE
107views Hardware» more  DATE 2006»
14 years 3 months ago
Flexible specification and application of rule-based transformations in an automotive design flow
This paper addresses an XML-based design environment, which provides a powerful basis for the manipulation of hardware design descriptions. The contribution of the paper is a flex...
Jan-Hendrik Oetjens, Joachim Gerlach, Wolfgang Ros...
DATE
2006
IEEE
108views Hardware» more  DATE 2006»
14 years 3 months ago
Software-friendly HW/SW co-simulation: an industrial case study
This paper proposes a novel HW/SW co-simulation approach that minimizes the impact on software designers. We propose a SystemC-based system that enables the software team to test ...
Juanjo Noguera, Luis Baldez, Narcis Simon, Lluis A...
DATE
2006
IEEE
109views Hardware» more  DATE 2006»
14 years 3 months ago
A single photon avalanche diode array fabricated in deep-submicron CMOS technology
We report the first fully integrated single photon avalanche diode array fabricated in 0.35µm CMOS technology. At 25µm, the pixel pitch achieved by this design is the smallest e...
Cristiano Niclass, Maximilian Sergio, Edoardo Char...
DATE
2006
IEEE
151views Hardware» more  DATE 2006»
14 years 3 months ago
Designing MRF based error correcting circuits for memory elements
As devices are scaled to the nanoscale regime, it is clear that future nanodevices will be plagued by higher soft error rates and reduced noise margins. Traditional implementation...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
DATE
2006
IEEE
111views Hardware» more  DATE 2006»
14 years 3 months ago
Extraction of defect density and size distributions from wafer sort test results
Defect density and defect size distributions (DDSDs) are key parameters used in IC yield loss predictions. Traditionally, memories and specialized test structures have been used t...
Jeffrey E. Nelson, Thomas Zanon, Rao Desineni, Jas...
DATE
2006
IEEE
110views Hardware» more  DATE 2006»
14 years 3 months ago
An improved RF loopback for test time reduction
In this work a method to improve the loopback test used in RF analog circuits is described. The approach is targeted to the SoC environment, being able to reuse system resources i...
Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Su...
DATE
2006
IEEE
78views Hardware» more  DATE 2006»
14 years 3 months ago
STAX: statistical crosstalk target set compaction
This paper presents STAX, a crosstalk target set compaction framework to reduce the complexity of the crosstalk ATPG process by pruning non-fault-producing targets. In general, ex...
Shahin Nazarian, Massoud Pedram, Sandeep K. Gupta,...
DATE
2006
IEEE
124views Hardware» more  DATE 2006»
14 years 3 months ago
Cell delay analysis based on rate-of-current change
Abstract - A cell delay model based on rate-of-currentchange is presented, which accounts for the impact of the shape of the noisy waveform on the output voltage waveform. More pre...
Shahin Nazarian, Massoud Pedram
DATE
2006
IEEE
88views Hardware» more  DATE 2006»
14 years 3 months ago
Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures
Temporal partitioning techniques are useful to implement large and complex applications, which can be split into partitions in FPGA devices. In order to minimize resources, each o...
Paulo Sérgio B. do Nascimento, Manoel Euseb...