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FPL
2007
Springer
190views Hardware» more  FPL 2007»
14 years 3 months ago
Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems
In this paper we present Minibit+, an approach that optimizes the bit-widths of fixed-point and floating-point designs, while guaranteeing accuracy. Our approach adopts differen...
William G. Osborne, Ray C. C. Cheung, José ...
FPL
2007
Springer
176views Hardware» more  FPL 2007»
14 years 3 months ago
ReconOS: An RTOS supporting Hard- and Software Threads
Modern platform FPGAs integrate fine-grained reconfigurable logic with processor cores and allow the creation of complete configurable systems-on-chip. However, design methodol...
Enno Lübbers, Marco Platzner
FPL
2007
Springer
94views Hardware» more  FPL 2007»
14 years 3 months ago
A Many-core Implementation based on the Reconfigurable Mesh Model
The reconfigurable mesh is a model for massively parallel computing for which many algorithms with very low complexity have been developed. These algorithms execute cycles of bus...
Heiner Giefers, Marco Platzner
FPL
2007
Springer
126views Hardware» more  FPL 2007»
14 years 3 months ago
A Time-Triggered Network-on-Chip
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
Martin Schoeberl
FPL
2007
Springer
178views Hardware» more  FPL 2007»
14 years 3 months ago
Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support
This paper introduces a software supported methodology for exploring/evaluating 3D FPGA architectures. Two new CAD tools are developed: (i) the 3DPRO for placement and routing on ...
Kostas Siozios, Kostas Sotiriadis, Vasilis F. Pavl...
FPL
2007
Springer
115views Hardware» more  FPL 2007»
14 years 3 months ago
Hardware/Software Process Migration and RTL Simulation
This paper describes an execution cache that uses process migration between hardware and software contexts by way of run-time reconfiguration (RTR) of Field Programmable Gate Arr...
Aric D. Blumer, Cameron D. Patterson
FPL
2007
Springer
128views Hardware» more  FPL 2007»
14 years 3 months ago
Embedded Programmable Logic Core Enhancements for System Bus Interfaces
Programmable logic cores (PLCs) offer a means of providing post-fabrication re-configurability to a SoC design. Circuits implemented in a PLC will inevitably have lower timing per...
Bradley R. Quinton, Steven J. E. Wilton
FPL
2007
Springer
198views Hardware» more  FPL 2007»
14 years 3 months ago
Floating-Point Trigonometric Functions for FPGAs
Field-programmable circuits now have a capacity that allows them to accelerate floating-point computing, but are still missing core libraries for it. In particular, there is a ne...
Jérémie Detrey, Florent de Dinechin