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ICCAD
2002
IEEE
141views Hardware» more  ICCAD 2002»
14 years 8 months ago
A hierarchical modeling framework for on-chip communication architectures
— The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication archite...
Xinping Zhu, Sharad Malik
ICCAD
2002
IEEE
98views Hardware» more  ICCAD 2002»
14 years 8 months ago
On-chip interconnect modeling by wire duplication
In this paper, we present a novel wire duplication-based interconnect modeling technique. The proposed modeling technique exploits the sparsity of the L 1 matrix, where L is the ...
Guoan Zhong, Cheng-Kok Koh, Kaushik Roy
ICCAD
2002
IEEE
113views Hardware» more  ICCAD 2002»
14 years 8 months ago
Interconnect-aware high-level synthesis for low power
Abstract—Interconnects (wires, buffers, clock distribution networks, multiplexers and busses) consume a significant fraction of total circuit power. In this work, we demonstrat...
Lin Zhong, Niraj K. Jha
ICCAD
2002
IEEE
92views Hardware» more  ICCAD 2002»
14 years 8 months ago
ECO algorithms for removing overlaps between power rails and signal wires
Design ECO commonly happens in industry due to constraints or target changes from manufacturing, marketing, reliability, or performance. At each step, designers usually want to mo...
Hua Xiang, Kai-Yuan Chao, D. F. Wong
ICCAD
2002
IEEE
146views Hardware» more  ICCAD 2002»
14 years 8 months ago
Conflict driven learning in a quantified Boolean Satisfiability solver
Within the verification community, there has been a recent increase in interest in Quantified Boolean Formula evaluation (QBF) as many interesting sequential circuit verification ...
Lintao Zhang, Sharad Malik
ICCAD
2002
IEEE
103views Hardware» more  ICCAD 2002»
14 years 8 months ago
A technology-independent CAD tool for ESD protection device extraction: ESDExtractor
The challenges for developing an ESD (Electro-static Discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extr...
Rouying Zhan, Haigang Feng, Qiong Wu, Guang Chen, ...
ICCAD
2002
IEEE
116views Hardware» more  ICCAD 2002»
14 years 8 months ago
Conflict driven techniques for improving deterministic test pattern generation
This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic de...
Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xiji...
ICCAD
2002
IEEE
71views Hardware» more  ICCAD 2002»
14 years 8 months ago
Timing-driven placement using design hierarchy guided constraint generation
Xiaojian Yang, Bo-Kyung Choi, Majid Sarrafzadeh
ICCAD
2002
IEEE
124views Hardware» more  ICCAD 2002»
14 years 8 months ago
Symbolic pointer analysis
— One of the bottlenecks in the recent movement of hardware synthesis from behavioral C programs is the difficulty in reasoning about runtime pointer values at compile time. The...
Jianwen Zhu
ICCAD
2002
IEEE
149views Hardware» more  ICCAD 2002»
14 years 8 months ago
Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step
─ In this paper, we present Forge, an optimal algorithm for gate sizing using the Elmore delay model. The algorithm utilizes Lagrangian relaxation with a fast gradient-based pre-...
Hiran Tennakoon, Carl Sechen