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ICCD
2006
IEEE
139views Hardware» more  ICCD 2006»
14 years 9 months ago
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
Sean Leventhal, Manoj Franklin
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
14 years 9 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
ICCD
2006
IEEE
77views Hardware» more  ICCD 2006»
14 years 9 months ago
Iterative-Constructive Standard Cell Placer for High Speed and Low Power
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
Sungjae Kim, Eugene Shragowitz
ICCD
2006
IEEE
171views Hardware» more  ICCD 2006»
14 years 9 months ago
Stochastic Dynamic Thermal Management: A Markovian Decision-based Approach
This paper proposes a stochastic dynamic thermal management (DTM) technique in high-performance VLSI system with especial attention to the uncertainty in temperature observation. ...
Hwisung Jung, Massoud Pedram
ICCD
2006
IEEE
103views Hardware» more  ICCD 2006»
14 years 9 months ago
Reduce Register Files Leakage Through Discharging Cells
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
Lingling Jin, Wei Wu, Jun Yang 0002, Chuanjun Zhan...
ICCD
2006
IEEE
121views Hardware» more  ICCD 2006»
14 years 9 months ago
Power/ground supply network optimization for power-gating
-- Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects on ...
Hailin Jiang, Malgorzata Marek-Sadowska
ICCD
2006
IEEE
131views Hardware» more  ICCD 2006»
14 years 9 months ago
Power-Constrained SOC Test Schedules through Utilization of Functional Buses
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 9 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
ICCD
2006
IEEE
96views Hardware» more  ICCD 2006»
14 years 9 months ago
An Enhancement for a Scheduling Logic Pipelined over two Cycles
Ruben Gran Tejero, Enric Morancho, Àngel Ol...
ICCD
2006
IEEE
115views Hardware» more  ICCD 2006»
14 years 9 months ago
Long-term Performance Bottleneck Analysis and Prediction
— Identifying performance bottlenecks is important for microarchitects and application developers to produce high performance microprocessor designs and application software. Man...
Fei Gao, Suleyman Sair