Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
This paper proposes a stochastic dynamic thermal management (DTM) technique in high-performance VLSI system with especial attention to the uncertainty in temperature observation. ...
— We propose a low-leakage register file cell design based on the observation that the physical registers in a superscalar processor have very short life cycles. When a register...
Lingling Jin, Wei Wu, Jun Yang 0002, Chuanjun Zhan...
-- Power-gating is a technique for efficiently reducing leakage power by shutting off the idle blocks. However, the presence of power-gating may also introduce negative effects on ...
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orail...
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
— Identifying performance bottlenecks is important for microarchitects and application developers to produce high performance microprocessor designs and application software. Man...