Sciweavers

ICCD
2006
IEEE
275views Hardware» more  ICCD 2006»
14 years 9 months ago
Split-Row: A Reduced Complexity, High Throughput LDPC Decoder Architecture
— A reduced complexity LDPC decoding method is presented that dramatically reduces wire interconnect complexity, which is a major issue in LDPC decoders. The proposed Split-Row m...
Tinoosh Mohsenin, Bevan M. Baas
ICCD
2006
IEEE
138views Hardware» more  ICCD 2006»
14 years 9 months ago
Delay and Area Efficient First-level Cache Soft Error Detection and Correction
—Soft error rates are an increasing problem in modern VLSI circuits. Commonly used error correcting codes reduce soft error rates in large memories and second level caches but ar...
Karl Mohr, Lawrence Clark
ICCD
2006
IEEE
123views Hardware» more  ICCD 2006»
14 years 9 months ago
Steady and Transient State Analysis of Gate Leakage Current in Nanoscale CMOS Logic Gates
Abstract— Gate leakage (direct tunneling current for sub65nm CMOS) can severely affect both the transient and steady state behaviors of CMOS circuits. In this paper we quantify t...
Saraju P. Mohanty, Elias Kougianos
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
14 years 9 months ago
Dynamic Co-Processor Architecture for Software Acceleration on CSoCs
By integrating one or more (hard or soft) CPU core on the chip, new generation platform FPGAs have become configurable systems on a chip (CSoC) that support a combined software an...
Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A...
ICCD
2006
IEEE
166views Hardware» more  ICCD 2006»
14 years 9 months ago
FPGA Implementation of High Speed FIR Filters Using Add and Shift Method
Shahnam Mirzaei, Anup Hosangadi, Ryan Kastner
ICCD
2006
IEEE
157views Hardware» more  ICCD 2006»
14 years 9 months ago
Statistical Analysis of Power Grid Networks Considering Lognormal Leakage Current Variations with Spatial Correlation
— As the technology scales into 90nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the vol...
Ning Mi, Jeffrey Fan, Sheldon X.-D. Tan
ICCD
2006
IEEE
127views Hardware» more  ICCD 2006»
14 years 9 months ago
CMOS Comparators for High-Speed and Low-Power Applications
— In this paper, we present two designs for CMOS comparators: one which is targeted for high-speed applications and another for low-power applications. Additionally, we present h...
Eric Menendez, Dumezie Maduike, Rajesh Garg, Sunil...
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
14 years 9 months ago
Fast, Performance-Optimized Partial Match Address Compression for Low-Latency On-Chip Address Buses
— The influence of interconnects on processor performance and cost is becoming increasingly pronounced with technology scaling. In this paper, we present a fast compression sche...
Jiangjiang Liu, Krishnan Sundaresan, Nihar R. Maha...
ICCD
2006
IEEE
126views Hardware» more  ICCD 2006»
14 years 9 months ago
Task Merging for Dynamic Power Management of Cyclic Applications in Real-Time Multi-Processor Systems
—In this paper we propose the method of task merging and idle period clustering for dynamic power management (DPM) in a real-time system with multiple processing elements. We sho...
Shaobo Liu, Qinru Qiu, Qing Wu
ICCD
2006
IEEE
115views Hardware» more  ICCD 2006»
14 years 9 months ago
Microarchitecture and Performance Analysis of Godson-2 SMT Processor
—This paper introduces the microarchitecture and logical implementation of SMT (Simultaneous Multithreading) improvement of Godson-2 processor which is a 64-bit, four-issue, out-...
Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang