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ICCD
2006
IEEE
182views Hardware» more  ICCD 2006»
14 years 9 months ago
A performance and power analysis of WK-Recursive and Mesh Networks for Network-on-Chips
—Network-on-Chip (NoC) has been proposed as an attractive alternative to traditional dedicated wires to achieve high performance and modularity. Power efficiency is one of the mo...
Dara Rahmati, Abbas Eslami Kiasari, Shaahin Hessab...
ICCD
2006
IEEE
86views Hardware» more  ICCD 2006»
14 years 9 months ago
Interconnect Matching Design Rule Inferring and Optimization through Correlation Extraction
— New back-end design for manufacturability rules have brought guarantee rules for interconnect matching. These rules indicate a certain capacitance matching guarantee given spac...
Rasit Onur Topaloglu, Andrew B. Kahng
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
14 years 9 months ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 9 months ago
A theory of Error-Rate Testing
— We have entered an era where chip yields are decreasing with scaling. A new concept called intelligible testing has been previously proposed with the goal of reversing this tre...
Shideh Shahidi, Sandeep Gupta
ICCD
2006
IEEE
96views Hardware» more  ICCD 2006»
14 years 9 months ago
An Efficient, Scalable Hardware Engine for Boolean SATisfiability
Mandar Waghmode, Kanupriya Gulati, Sunil P. Khatri...
ICCD
2006
IEEE
312views Hardware» more  ICCD 2006»
14 years 9 months ago
A Design Approach for Fine-grained Run-Time Power Gating using Locally Extracted Sleep Signals
— Leakage power dissipation becomes a dominant component in operation power in nanometer devices. This paper describes a design methodology to implement runtime power gating in a...
Kimiyoshi Usami, Naoaki Ohkubo
ICCD
2006
IEEE
189views Hardware» more  ICCD 2006»
14 years 9 months ago
A Capacity Co-allocation Configurable Cache for Low Power Embedded Systems
— Traditional level-one instruction caches and data caches for embedded systems typically have the same capacities. Configurable caches either shut down a part of the cache to su...
Chuanjun Zhang
ICCD
2006
IEEE
113views Hardware» more  ICCD 2006»
14 years 9 months ago
High-speed Factorization Architecture for Soft-decision Reed-Solomon Decoding
Reed-Solomon (RS) codes are among the most widely utilized error-correcting codes in modern communication and computer systems. Among the decoding algorithms of RS codes, the rece...
Xinmiao Zhang
ICCD
2006
IEEE
121views Hardware» more  ICCD 2006»
14 years 9 months ago
A Low Power Highly Associative Cache for Embedded Systems
—Reducing energy consumption is an important issue for battery powered embedded computing systems. Content Addressable Memory (CAM)-based Highly-Associative Caches (HAC) are wide...
Chuanjun Zhang