ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract— In this paper, we propose a novel common subexpresson elimination (CSE) method to be used for VLSI design of multiplierless finite impulse response (FIR) filter with ...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— A novel method to extract the efficient model for Metal-Oxide-Semiconductor (MOS) transistors in order to satisfy a specific accuracy is presented. The approach presented here ...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— Low-Density Parity-Check Convolutional Codes (LDPC-CCs) are an attractive alternative to their block-oriented counterparts, LDPC-BCs. In this paper, we introduce these codes an...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— The paper describes a 4-MHz temperature compensated reference oscillator based on a capacitive silicon micro-mechanical resonator. The design of the resonator has been optimize...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
—This paper describes a 20-Gb/s continuous-time adaptive passive equalizer utilizing on-chip lumped RLC components. Passive equalizers offer the advantages of higher bandwidth an...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— In this paper, we focus on the problem of designing an energy efficient MAC protocol for wireless sensor networks and propose a novel scheme, named as TEEM (Traffic aware, Ener...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract— Practical log-domain filter circuits might have multiple operating points in regions in which the translinear element does not obey the exponential law. In this paper,...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— This paper presents the design of a combined two’s complement and IEEE 754-compliant floating-point comparator. Unlike previous designs, this comparator incorporates both op...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
In this paper, a framework of designing a low-error and power-efficient two’s-complement fixed-width Booth multiplier that receives two n-bit numbers and produces an n-bit produ...