ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
-- Timing optimization is an important goal of global routing in deep submicron era. To guarantee the timing performance of the circuit, merely adopting topology optimization becom...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
—We present a Built-In Self-Test (BIST) approach based on direct digital synthesizer (DDS) for functionality testing of analog circuitry in mixed-signal systems. DDS with Delta-S...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
In high-level synthesis, accurate lower-bound estimation is helpful to explore the search space efficiently and to evaluate the quality of heuristic algorithms. For the lower-bound...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— This paper presents a scheme for testing DACs’ static non-linearity errors by using a two-step flash ADC with deterministic dynamic element matching (DDEM). In this work, the...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
— In this paper, we propose a new random-valued impulse noise detector from images using level detection. In our method, we use directional windows in order to search a level reg...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
Abstract— This paper describes the fast-scale bifurcation phenomena of a single-stage power-factor-correction (PFC) power supply which is commonly used in low power applications....
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
—This paper proposes a new switching architecture to be used in all optical networks. The proposed switch, M-B-Quadro switch, is extended from an original 2 x 2 two-stage multi-b...
ISCAS
2005
IEEE
14 years 5 months ago
2005
IEEE
