— With the transition to deep submicron technologies the density of on-chip interconnect lines has increased, together with the switching rate of the signals propagating along th...
Abstract— This paper presents a new oversampling architecture for implementing phase-tracking loop that is commonly utilized for position sensors such that synchro, resolver, and...
—In this paper we propose an analog VLSI approach to maximum a posteriori (MAP) detection in Multiple-Input Multiple-Output (MIMO) systems. This detector can be seen as an extens...
Josep Soler Garrido, Robert J. Piechocki, K. Mahar...
—This paper presents a high-performance CAVLC decoding VLSI architecture for MPEG-4 AVC/H.264. Instead of just skipping zero block, the proposed design explores the features of C...
Extremely low power consumption is the critical constraint for designing implantable neural decoders that inter- Desired face directly with the nervous system. Typically a system w...
Abstract— We present a simple silicon circuit for modelling voltagedependent ion channels found within neural cells, capturing both the gating particle’s sigmoidal activation (...
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
Stephen Bates, L. Gunthorpe, Ali Emre Pusane, Zhen...
A robust system architecture to achieve optical coherency free optimization. Several methods that had been proposed in the in multiple-beam free-space laser communication links wit...
Dimitrios N. Loizos, Paul-Peter Sotiriadis, Gert C...
— an efficient rate-distortion (R-D) optimal method for transcoding hierarchical B-pictures is proposed in this paper. A new R-D model is presented for fast transcoding hierarchi...
— The implementation of a high-performance network-on-chip (NoC) requires an efficient design for the network interface unit (NIU) that connects the switched network to the IP c...