Sciweavers

DSD
2007
IEEE
160views Hardware» more  DSD 2007»
14 years 5 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
DATE
2007
IEEE
85views Hardware» more  DATE 2007»
14 years 5 months ago
Low-power warp processor for power efficient high-performance embedded systems
Researchers previously proposed warp processors, a novel architecture capable of transparently optimizing an executing application by dynamically re-implementing critical kernels ...
Roman L. Lysecky
VTC
2008
IEEE
113views Communications» more  VTC 2008»
14 years 5 months ago
Non-Linear UWB Receivers with MLSE Post-Detection
— A wireless body area network with an average throughput of 500 kbps is considered based on ultra-wideband (UWB) pulse position modulation. For a long battery autonomy ultra low...
Florian Troesch, Thomas Zasowski, Armin Wittneben
VLSID
2008
IEEE
142views VLSI» more  VLSID 2008»
14 years 5 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significa...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
SOCC
2008
IEEE
121views Education» more  SOCC 2008»
14 years 5 months ago
Low power 8T SRAM using 32nm independent gate FinFET technology
In this paper, new SRAM cell design methods for FinFET technology are proposed. One of the most important features of FinFET is that the independent front and back gate can be bia...
Young Bok Kim, Yong-Bin Kim, Fabrizio Lombardi
ISCAS
2008
IEEE
103views Hardware» more  ISCAS 2008»
14 years 5 months ago
A low-power monolithically stacked 3D-TCAM
—This paper presents three techniques to reduce the power consumption in ternary content-addressable memories (TCAMs). The first technique is to use newly developed monolithical...
Mingjie Lin, Jianying Luo, Yaling Ma
ISCAS
2008
IEEE
112views Hardware» more  ISCAS 2008»
14 years 5 months ago
Power optimization of weighted bit-product summation tree for elementary function generator
— In this paper we propose a method for lowering the power consumption in our previously proposed method for approximating elementary functions. By rearranging the interconnect o...
Saeeid Tahmasbi Oskuii, Kenny Johansson, Oscar Gus...
IPPS
2008
IEEE
14 years 5 months ago
Energy efficient packet classification hardware accelerator
Packet classification is an important function in a router’s line-card. Although many excellent solutions have been proposed in the past, implementing high speed packet classifi...
Alan Kennedy, Xiaojun Wang, Bin Liu
IPPS
2008
IEEE
14 years 5 months ago
Modeling and analysis of power in multicore network processors
With the emergence of multicore network processors in support of high-performance computing and networking applications, power consumption has become a problem of increasing signi...
S. Huang, Y. Luo, W. Feng
INFOCOM
2008
IEEE
14 years 5 months ago
Power Awareness in Network Design and Routing
Abstract—Exponential bandwidth scaling has been a fundamental driver of the growth and popularity of the Internet. However, increases in bandwidth have been accompanied by increa...
Joseph Chabarek, Joel Sommers, Paul Barford, Crist...