SBCCI
2004
ACM
14 years 27 days ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
DFT
2006
IEEE
14 years 1 months ago
2006
IEEE
1 High temperature has become a major problem for system-on-chip testing. In order to reduce the test time while keeping the temperature of the chip under test within a safe range,...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
The test time for core-external interconnect shorts/opens is typically much less than that for core-internal logic. Therefore, prior work on test infrastructure design for core-ba...