VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
The improved T and improved n models are proposed for onchip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeli...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
In this paper, we propose a hierarchical timing-driven Steiner tree algorithm for global routing which considers the minimization of timing delay during the tree construction as t...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
This paper presents a novel technique, called input space adaptive software synthesis, for the energy and performance optimization of embedded software. The proposed technique is ...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
In floorplan design, it is common that a designer will want to control the positions of some modules in the final packing for various purposes like data path alignment, I/O connec...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
External pins for test are precious hardware resources because this number is strongly restricted. Cores are tested via test access mechanisms (TAMs) such as a test bus architectu...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Various calculation of matrices and vectors has been used in many digital signal processing systems. Although the calculation simply repeats multiplication and addition, the reite...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
We present an efficient implementation of an approximate balanced truncation model reduction technique for general large-scale RLC systems, described by a statespace model where t...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes ...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Critical issues in designing a high speed, low power static RAM in deep submicron technologies are described along with the design techniques used to overcome them. With appropria...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power ...