VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
With the increased use of embedded/portable devices such as smart cellular phones, pagers, PDAs, hand-held computers, and CD players, improving energy efficiency is becoming a cri...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
If motion estimation can choose the most suitable algorithm according to the changing characteristics of input image signals, we can get benefits, which improve quality and perfor...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
The radiation and surface wave losses may give rise to electromagnetic interference (EMI) problems in high speed VLSI interconnects. Over and above there will be dielectric and co...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
In preemptive real-time systems, a tighter estimate of the Worst Case Response Time(WCRT) of the tasks can be obtained if the layout of the tasks in memory is included in the esti...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Microprocessors with built-in Liquid Crystal Device (LCD) controllers and equipped with Flash ROM are common in mobile computing applications. In the first part of the paper, a so...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Compare CMOS Logic with Pass-Transistor Logic, a question was raised in our mind: "Does any rule exist that contains all good?" This paper reveals novel logic synthesis ...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Interconnect delay has become a critical factor in determining the performance of integrated circuits. Routing and buffering are powerful means of improving the circuit speed and ...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Steiner tree is a fundamental problem in the automatic interconnect optimization for VLSI design. We present a probabilistic analysis method for constructing rectilinear Steiner t...
VLSID
2002
IEEE
15 years 25 days ago
2002
IEEE
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...