Sciweavers

DATE
2008
IEEE

Latch Modeling for Statistical Timing Analysis

14 years 7 months ago
Latch Modeling for Statistical Timing Analysis
—Latch based circuits are widely adopted in high performance circuits. But there is a lack of accurate latch models for doing timing analysis. In this paper, we propose a new latch delay model in the context of SSTA based on a new perspective of latch timing. The proposed latch model also takes into account the external timing variations such as data slew. The new latch model is integrated into SSTA by considering the timing analysis of both the combinational logic network and the clock distribution network simultaneously. The experimental results show that ignoring accurate latch modeling may lead to large errors (e.g., 50% at PDF peak).
Sean X. Shi, Anand Ramalingam, Daifeng Wang, David
Added 29 May 2010
Updated 29 May 2010
Type Conference
Year 2008
Where DATE
Authors Sean X. Shi, Anand Ramalingam, Daifeng Wang, David Z. Pan
Comments (0)