103 search results - page 13 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
ISCAS
2007
IEEE
14 years 2 months ago
2007
IEEE
Due to the development of high speed circuits beyond the 2-GHz mark, the significance of automatic test pattern generation for Path Delay Faults (PDFs) drastically increased in t...
ASPLOS
2006
ACM
14 years 1 months ago
2006
ACM
The sustained push toward smaller and smaller technology sizes has reached a point where device reliability has moved to the forefront of concerns for next-generation designs. Sil...
ET
2010
13 years 6 months ago
2010
Abstract As technology scales down into the nanometer era, delay testing of modern chips has become more and more important. Tests for the path delay fault model are widely used to...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
The presence of unknown values in the simulation result is a key barrier to effective output response compaction in practice. This paper proposes a simple circuit module, called a...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Built-in self-repair (BISR) technique is gaining popular for repairing embedded memory cores in system-onchips (SOCs). To increase the utilization of memory redundancy, the BISR t...