103 search results - page 9 / 21 » A Fault Modeling Technique to Test Memory BIST Algorithms |
ITC
2003
IEEE
14 years 1 months ago
2003
IEEE
Embedded memories are among the most widely used cores in current system-on-chip (SOC) implementations. Memory cores usually occupy a significant portion of the chip area, and do...
ICCAD
1994
IEEE
13 years 12 months ago
1994
IEEE
The BIST implementation of a conventionally synthesized controller in most cases requires the integration of an additional register only for test purposes. This leads to some seri...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
In this paper, we compare embedded-DRAM (eDRAM) testing to both SRAM testing and commodity-DRAM testing, since an eDRAM macro uses DRAM cells with an SRAM interface. We first star...
ISMVL
2007
IEEE
14 years 2 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
JSS
2008
13 years 6 months ago
2008
This report presents a model-driven, stress test methodology aimed at increasing chances of discovering faults related to network traffic in Distributed Real-Time Systems (DRTS). T...