48 search results - page 5 / 10 » A General Algorithm for Tiling the Register Level |
DAC
2008
ACM
14 years 9 months ago
2008
ACM
We present a domain-specific approach to representing datapaths for hardware implementations of linear signal transform algorithms. We extend the tensor structure for describing l...
CODES
2005
IEEE
14 years 2 months ago
2005
IEEE
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
CC
2008
Springer
13 years 10 months ago
2008
Springer
The polyhedral model provides powerful abstractions to optimize loop nests with regular accesses. Affine transformations in this model capture a complex sequence of execution-reord...
CODES
2007
IEEE
14 years 2 months ago
2007
IEEE
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
TVLSI
2010
13 years 3 months ago
2010
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...