136 search results - page 10 / 28 » A Graph Reduction Approach to Symbolic Circuit Analysis |
ASPDAC
2007
ACM
13 years 11 months ago
2007
ACM
With semiconductor fabrication technologies scaled below 100 nm, the design-manufacturing interface becomes more and more complicated. The resultant process variability causes a nu...
ICCAD
2005
IEEE
14 years 4 months ago
2005
IEEE
State-equivalence based reduction techniques, e.g. bisimulation minimization, can be used to reduce a state transition system to facilitate subsequent verification tasks. However...
EDBT
2012
ACM
11 years 10 months ago
2012
ACM
In this paper, we study how to find maximal k-edge-connected subgraphs from a large graph. k-edge-connected subgraphs can be used to capture closely related vertices, and findin...
ISQED
2009
IEEE
14 years 2 months ago
2009
IEEE
— With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally ef...
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Level-sensitive transparent latches are widely used in high-performance sequential circuit designs. Under process variations, the timing of a transparently latched circuit will ada...