21 search results - page 3 / 5 » A Graph-Theoretic Approach to Clock Skew Optimization |
ISPD
1999
ACM
13 years 12 months ago
1999
ACM
Buffer insertion is an effective approach to achieve both minimal clock signal delay and skew in high speed VLSI circuit design. In this paper, we develop an optimal buffer ins...
DAC
2008
ACM
13 years 9 months ago
2008
ACM
Clock skew scheduling has been traditionally considered as a tool for improving the clock period in a sequential circuit. Timing slack is "stolen" from fast combinationa...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...
ICCAD
2004
IEEE
14 years 4 months ago
2004
IEEE
Traditional timing-driven placement considers only combinational delays and does not take into account the potential of subsequent sequential optimization steps. As a result, the ...
ICCAD
2010
IEEE
13 years 5 months ago
2010
IEEE
Clock mesh is popular in high performance VLSI design because it is more robust against variations than clock tree at a cost of higher power consumption. In this paper, we propose ...