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» A Low Power Approach to Floating Point Adder Design
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ICCD
1997
IEEE
115views Hardware» more  ICCD 1997»
14 years 2 months ago
A Low Power Approach to Floating Point Adder Design
R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Kha...
ASAP
2004
IEEE
115views Hardware» more  ASAP 2004»
14 years 1 months ago
A Low-Power Carry Skip Adder with Fast Saturation
In this paper, we present the design of a carry skip adder that achieves low power dissipation and high-performance operation. The carry skip adder's delay and power dissipat...
Michael J. Schulte, Kai Chirca, John Glossner, Hao...
TC
2010
13 years 8 months ago
Redundant-Digit Floating-Point Addition Scheme Based on a Stored Rounding Value
—Due to the widespread use and inherent complexity of floating-point addition, much effort has been devoted to its speedup via algorithmic and circuit techniques. We propose a ne...
Ghassem Jaberipur, Behrooz Parhami, Saeid Gorgin
VLSID
2006
IEEE
145views VLSI» more  VLSID 2006»
14 years 3 months ago
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format
IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. This paper proposes two novel ...
Himanshu Thapliyal, Saurabh Kotiyal, M. B. Sriniva...
ARITH
2007
IEEE
14 years 4 months ago
Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding
Shrinking feature sizes gives more headroom for designers to extend the functionality of microprocessors. The IEEE 754R working group has revised the IEEE 754-1985 Standard for Bi...
Liang-Kai Wang, Michael J. Schulte