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» A Methodology for Large-Scale Hardware Verification
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CODES
2005
IEEE
14 years 3 months ago
Comparing two testbench methods for hierarchical functional verification of a bluetooth baseband adaptor
The continuous improvement on the design methodologies and processes has made possible the creation of huge and very complex digital systems. Design verification is one of the mai...
Edgar L. Romero, Marius Strum, Wang Jiang Chau
ISPD
1997
ACM
100views Hardware» more  ISPD 1997»
14 years 2 months ago
A pseudo-hierarchical methodology for high performance microprocessor design
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
A. Bertolet, K. Carpenter, Keith M. Carrig, Albert...
HICSS
2006
IEEE
164views Biometrics» more  HICSS 2006»
14 years 3 months ago
A Methodology for Generating Application-Specific Heterogeneous Processor Arrays
Hardware designers are increasingly turning to Single Chip Multi-Processors to achieve power and throughput goals. To further increase performance for a specific application the c...
Stephen D. Craven, Cameron Patterson, Peter M. Ath...
ASPDAC
2007
ACM
101views Hardware» more  ASPDAC 2007»
14 years 1 months ago
A New Methodology for Interconnect Parasitics Extraction Considering Photo-Lithography Effects
Abstract-- Due to photo-lithography effects and manufacture process variations, the actual features fabricated on the wafer are different from the designed ones. This difference ca...
Ying Zhou, Zhuo Li, Yuxin Tian, Weiping Shi, Frank...
DATE
2004
IEEE
134views Hardware» more  DATE 2004»
14 years 1 months ago
Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor
ASIC designs for future communication applications cannot be simulated exhaustively. Formal Property Checking is a powerful technology to overcome the limitations of current funct...
Klaus Winkelmann, Hans-Joachim Trylus, Dominik Sto...